STSR2 データシートの表示（PDF） - STMicroelectronics

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STSR2

FORWARD SYNCHRONOUS RECTIFIERS SMART DRIVER

STMicroelectronics 

STSR2

PIN DESCRIPTION

Pin N°

1

Symbol

OUTGATE1

2

VCC

3

SETANT2

4

CK

5

INHIBIT

6

SGLGND

7

OUTGATE2

8

PWRGND

Name and Function

Gate Drive signal for Rectifier MOSFET. Anticipation (tANT1) in turning off

OUTGATE1 is provided when the clock input goes to low level.

The supply voltage range from 4.5V to 5.5V allows applications with logic gate

threshold mosfets. UVLO feature guarantees proper start-up while it avoids

undesirable driving during eventual dropping of the supply voltage.

The voltage on this pin sets the anticipation (tANT1) in turning off the OUTGATE2. It

is possible to choose among three different anticipation times by discrete

partitioning of the supply voltage.

This input provides synchronization for IC’s operations, being the transitions

between the two output conditions based on a positive threshold, equal for the

two slopes. A smart internal control logic mechanism using a 15MHz internal

oscillator generates proper anticipation timing at the turn-off of each output. This

feature allows safe turn-off of Synchronous Rectifiers avoiding any eventual

shoot-through situation on secondary side at both transitions. Smart clock

revelation mechanism makes these operations independent by false triggering

pulses generated in light load conditions and by particular demagnetization

techniques.Absolute maximum voltage rating of the pin can be exceeded limiting

the current flowing into the pin to 10mA max.

This input enables OUTGATE2 to work when its voltage is lower than the negative

threshold voltage (VINHIBIT<VH). If VINHIBIT>VH the OUTGATE2 will be high for a

minimum conduction time (tON(GATE2)). In typical forward converter application, it

is possible to turn off the freewheeling MOSFET when the current through it tends

to reverse, allowing discontinuous conduction mode and providing protection to

the converter from eventual sinking current from the load.Absolute maximum

voltage rating of the pin can be exceeded limiting the current flowing into the pin

to 10mA max.

Reference for all the control logic signals. This pin is completely separated from

the PWRGND to prevent eventual disturbances to affect the control logic.

Gate Drive signal for Freewheeling MOSFET. Anticipation [tANT2] in turning off

OUTGATE2 is provided when the clock input goes to high level.

Reference for power signals, this pin carries the full peak currents for the two

outputs.

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