STK25C48-45 データシートの表示（PDF） - Unspecified
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STK25C48-45 Datasheet PDF : 8 Pages
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STK25C48
DEVICE OPERATION
The STK25C48 is a versatile memory chip that pro-
vides several modes of operation. The STK25C48
can operate as a standard 8K x 8 SRAM. It has an
8K x 8 EEPROM shadow to which the SRAM informa-
tion can be copied, or from which the SRAM can be
updated in nonvolatile mode.
NOISE CONSIDERATIONS
Note that the STK25C48 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1µF connected between VCC
and VSS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK25C48 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-10 determines which of the 2,048 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high or W is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
AutoStore™ OPERATION
The STK25C48 uses the intrinsic system capaci-
tance to perform an automatic store on power down.
As long as the system power supply takes at least
tSTORE to decay from VSWITCH down to 3.6V, the
STK25C48 will safely and automatically store the
SRAM data in EEPROM on power down.
In order to prevent unneeded STORE operations,
automatic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle.
POWER-UP RECALL
During power up, or after any low-power condition
(VCC < VRESET), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK25C48 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
HARDWARE PROTECT
The STK25C48 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs
during low-voltage conditions. When VCC < VSWITCH,
STORE operations and SRAM WRITEs are inhibited.
LOW AVERAGE ACTIVE POWER
The STK25C48 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK25C48 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the VCC level; and 7) I/O loading.
July 1999
3-36
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