AD7664 データシートの表示（PDF） - Analog Devices
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AD7664 Datasheet PDF : 24 Pages
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PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
AGND 1
AVDD 2
NC 3
DGND 4
OB/2C 5
WARP 6
IMPULSE 7
SER/PAR 8
D0 9
D1 10
D2 11
D3 12
PIN 1
IDENTIFIER
AD7664
TOP VIEW
(Not to Scale)
36 AGND
35 CNVST
34 PD
33 RESET
32 CS
31 RD
30 DGND
29 BUSY
28 D15
27 D14
26 D13
25 D12
NC = NO CONNECT
13 14 15 16 17 18 19 20 21 22 23 24
AD7664
Pin No. Mnemonic
1
2
3, 40–42,
44–48
4
5
AGND
AVDD
NC
DGND
OB/2C
Type
P
P
DI
DI
6
WARP
DI
7
8
9–12
13
IMPULSE DI
SER/PAR
DI
D[0:3]
DO
D4
DI/O
or EXT/INT
14
D5
DI/O
or INVSYNC
15
D6
DI/O
or INVSCLK
PIN FUNCTION DESCRIPTIONS
Description
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 5 V.
No Connect.
Must Be Tied to the Ground Where DVDD Is Referred.
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a twos complement output from
its internal shift register.
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the
maximum throughput is achievable, and a minimum conversion rate must be applied in order
to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of
the minimum conversion rate.
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In
this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the
Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port.
Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless
of the state of SER/PAR.
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal
clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is
synchronized to an external clock signal connected to the SCLK input.
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state
of the SYNC signal. It is active in both Master and Slave Mode. When LOW, SYNC is active
HIGH. When HIGH, SYNC is active LOW.
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal.
It is active in both Master and Slave Mode.
REV. E
–5–
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