SPT5400 データシートの表示（PDF） - Cadeka Microcircuits LLC.
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SPT5400 Datasheet PDF : 8 Pages
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
VDD to GND ............................................. –0.3 to +6 V
VSS to GND ............................................. –6 to +0.3 V
AGNDxx ..................... (GND – 0.3 V) to (VDD + 0.3 V)
Input Voltages
Digital Input Voltage to GND .. –0.3 V to (VDD + 0.3 V)
REFxx .................. (AGNDxx – 0.3 V) to (VDD + 0.3 V)
Maximum Current into REFxx Pin ................. ±10 mA
Output
VOUTxx ...................................................... VDD to VSS
Temperature
Operating Temperature, Ambient .............. 0 to +70 °C
Junction Temperature .................................... +165 °C
Lead Temperature, (soldering 10 seconds) ... +300 °C
Storage Temperature .......................... –65 to +150 °C
Power Dissipation ....................................... 1000 mW
Note 1: Operation at any Absolute Maximum Rating is not implied. Operation beyond the ratings may cause damage to the
device. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
VDD = +5 V, VSS = –5 V, REFxx = 4.096 V, AGNDxx = GND = 0 V, RL = 10 kΩ, CL = 50 pF, TA = TMIN to TMAX, unless otherwise
specified. Typical values are at TA = +25 °C.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
SPT5400
MIN
TYP
MAX UNITS
DC Performance
Resolution
Integral Linearity
Differential Linearity
Zero Code Error1
Gain Error2
Power Supply Rejection Ratio3
∆Gain/∆VDD
∆Gain/∆VSS
Load Regulation
Reference Input
Ref Input Range4,5
Ref Input Resistance5
Analog Output
Maximum Output Voltage
Minimum Output Voltage
Output Slew Rate
Output Settling Time6
Digital Feedthrough
Digital Crosstalk
Digital Inputs (VDD = 5 V ±5%)
Input Voltage High
Input Voltage Low
Input Current (VIN = 0 V or VDD)
Input Capacitance
VI
Guaranteed Monotonic
VI
VI
VI
VI
VI
RL = ∞ to 10 kΩ
V
IV
VI
V
V
V
To ±1/2 LSB of Full Scale V
V
V
VI
VI
VI
IV
13
Bits
±0.5
±4.0 LSB
±1.0 LSB
±10.0
±20 LSB
±1.0
±15 LSB
±0.0025 %/%
±0.0025 %/%
±0.4
LSB
AGND
5
VDD
V
kΩ
VDD – 0.5
VSS + 0.5
2.4
7.0
5
50
V
V
V/µs
µs
nV-s
nV-s
2.4
V
0.8
V
10.0 µA
10
pF
Power Supplies
Positive Supply Range (VDD)
Negative Supply Range (VSS)
Positive Supply Current
Negative Supply Current
Power Dissipation7
VI
4.75
5.25 V
VI
–5.25
–4.75 V
VI
15
25
mA
VI
16
25
mA
VI
155
250 mW
1Deviation of actual DAC output when all 0s are loaded to the DAC from the ideal output of –4.096 V.
2Deviation of actual DAC output span from the ideal span of 8.191 V.
3PSSR is tested by changing the respective supply voltage by ±5%.
4For best performance, REF should be greater than AGND + 2 V and less than VDD – 0.6 V. The device operates
with reference inputs outside this range, but performance may degrade.
5Reference input resistance is code dependent.
6Typical settling time with 1000 pF capacitive load is 8 µs.
7Does not include reference power.
SPT5400
2
5/15/00
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