AD7846KNZ データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
一致するリスト
AD7846KNZ Datasheet PDF : 24 Pages
| |||
AD7846
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DB2 1
28 DB3
DB1 2
27 DB4
DB0 3
26 DB5
VDD 4
25 LDAC
VOUT
RIN
VREF+
VREF–
VSS
5
24 CLR
6 AD7846 23 CS
7 TOP VIEW 22 R/W
8 (Not to Scale) 21 VCC
9
20 DGND
DB15 10
19 DB6
DB14 11
18 DB7
DB13 12
17 DB8
DB12 13
16 DB9
DB11 14
15 DB10
Figure 7. PDIP Pin Configuration
4 3 2 1 28 27 26
VOUT 5
RIN 6
VREF+ 7
VREF– 8
VSS 9
DB15 10
DB14 11
PIN 1
IDENTIFIER
AD7846
TOP VIEW
(Not to Scale)
25 LDAC
24 CLR
23 CS
22 R/W
21 VCC
20 DGND
19 DB6
12 13 14 15 16 17 18
Figure 8. CERDIP Pin Configuration
Table 5. Pin Function Descriptions
Pin
Mnemonic Description
1 to 3 DB2 to DB0 Data I/Os. DB0 is LSB.
4
VDD
5
VOUT
6
RIN
7
VREF+
Positive Supply for Analog Circuitry. This is +15 V nominal.
DAC Output Voltage.
Input to Summing Resistor of DAC Output Amplifier. This is used to select output voltage ranges. See Table 6.
VREF+ Input. The DAC is specified for VREF+ = +5 V.
8
VREF−
VREF− Input. For unipolar operation connect VREF− to 0 V, and for bipolar operation connect it to −5 V. The device is
specified for both conditions.
9
VSS
Negative Supply for the Analog Circuitry. This is −15 V nominal.
10 to 19 DB15 to DB6 Data I/Os. DB15 is MSB.
20
DGND
Ground for Digital Circuitry.
21
VCC
22
R/W
Positive Supply for Digital Circuitry. This is +5 V nominal.
R/W Input. This pin can be used to load data to the DAC or to read back the DAC latch contents.
23
CS
Chip Select Input. This pin selects the device.
24
CLR
Clear Input. The DAC can be cleared to 000…000 or 100…000. See Table 7.
25
LDAC
Asynchronous Load Input to DAC.
26 to 28 DB5 to DB3 Data I/Os.
Table 6. Output Voltage Ranges
Output Range
0 V to +5 V
0 V to +10 V
+5 V to −5 V
+5 V to −5 V
+10 V to −10 V
VREF+
+5 V
+5 V
+5 V
+5 V
+5 V
VREF−
0V
0V
−5 V
0V
−5 V
RIN
VOUT
0V
VOUT
+5 V
0V
Rev. G | Page 7 of 24
Share Link: 