PST600IM データシートの表示（PDF） - Mitsumi

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PST600IM

System Reset Monolithic IC

Mitsumi 

MITSUMI

IOL vs. Ta

60

50

IOL 40

(mA) 30

20

10

-40 -20 0

20 40 60 80

Ta (°C)

ICCL (IOL=0mA) vs. Ta

9

8

ICCL 7

(µA) 6

5

4

-40 -20 0

20 40 60 80

Ta (°C)

System Reset PST600

VOL vs. IOL

500

400

VOL 300

(mV) 200

100

0

0 2 4 6 8 10 12

IOL (mA)

Application Circuits

1. Normal hard reset

Delay Time (tPLH)

[ ] =··CL RL

ln

——————V—CC—————

VCC- (VS CPU+0.2)

+0.040 (mS)

CL : µF

Vs CPU : CPU, MPU reset threshold voltage

RL : kΩ

Voltage : V

Note : When VCC line impedance is high, connect a

capacitor between IC Pins 1 and 2.

2. Manual Reset

Note : Prevent Manual SW chattering by using RL , CL

and Rm. Rm setting conditions are as follows :

Rm <= 1/20 RL

Note : When VCC line impedance is high,connect a

capacitor between IC Pins 1 and 2.

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