MK2049-01 データシートの表示（PDF） - Integrated Circuit Systems
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MK2049-01 Datasheet PDF : 11 Pages
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MK2049-01
Communications Clock PLL
Pin Assignment
FS1 1
X2 2
X1 3
VDD 4
VDD 5
VDD 6
GND 7
CLK2 8
CLK1 9
8K 10
20 FS0
19 GND
18 CAP2
17 GND
16 CAP1
15 VDD
14 GND
13 ICLK
12 FS3
11 FS2
20 pin (300 mil) SOIC
Output Decoding Table – External Mode (MHz)
Input
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3 FS2 FS1 FS0
0000
0001
0010
0011
0111
CLK1
1.544
2.048
22.368
17.184
19.44
CLK2
3.088
4.096
44.736
34.368
38.88
Crystal
12.288
12.288
12.288
12.288
12.96
Output Decoding Table – Loop Timing Mode (MHz)
Input
1.544
2.048
44.736
34.368
FS3 FS2 FS1 FS0
1000
1001
1010
1011
CLK1
1.544
2.048
22.368
17.184
CLK2
3.088
4.096
44.736
34.368
Crystal
12.288
12.288
12.288
12.288
Pin Descriptions
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is applied to pins 2 and 3; clock input is applied to pin 13.
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
FS1
X2
X1
VDD
VDD
VDD
GND
CLK2
CLK1
8K
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
GND
FS0
Type Description
I Frequency Select 1. Determines CLK input/outputs per tables above.
O Crystal conection. Connect to a 12.288 MHz or 12.96 MHz crystal.
I Crystal conection. Connect to a 12.288 MHz or 12.96 MHz crystal.
P Connect to +5V.
P Connect to +5V.
P Connect to +5V.
P Connect to ground.
O Clock 2 output determined by status of FS3:0 per tables above.
O Clock 1 output determined by status of FS3:0 per tables above. CLK2 divided by 2.
O Recovered 8 kHz clock output. On External mode only.
I Frequency Select 2. Determines CLK input/outputs per tables above.
I Frequency Select 3. Determines CLK input/outputs per tables above.
I Input clock connection. Connect to 8 kHz backplane or to Loop Timing clock.
P Connect to ground.
P Connect to +5V.
LF Connect a 0.030 µF ceramic capacitor and a 7.5 MΩ resistor in series between this pin and CAP2.
P Connect to ground.
LF Connect a 0.030 µF ceramic capacitor and a 7.5 MΩ resistor in series between this pin and CAP1.
P Connect to ground.
I Frequency Select 0. Determines CLK input/outputs per tables above.
Type: I = Input, O = output, P = power supply connection, LF = loop filter connection
MDS 2049-01 J
2
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
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