MAX5392 データシートの表示（PDF） - Maxim Integrated
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MAX5392 Datasheet PDF : 16 Pages
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Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V,
TA = +25NC.) (Note 1)
PARAMETER
Data Setup Time
Data Hold Time
SDA, SCL Rise Time
SDA, SCL Fall
Setup Time for STOP Condition
Bus Free Time Between STOP and
START Condition
SYMBOL
tSU:DAT
tHD:DAT
tR
tF
tSU:STO
CONDITIONS
tBUF Minimum power-up rate = 0.2V/Fs
MIN
TYP MAX UNITS
100
ns
0
Fs
0.3
Fs
0.3
Fs
0.6
Fs
1.3
Fs
Pulse Suppressed Spike Width
Capacitive Load for Each Bus
tSP
CB
(Note 9)
50
ns
400
pF
Note 1: All devices are 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design
and characterization.
Note 2: DNL and INL are measured with the potentiometer configured as a voltage-divider (Figure 1) with H_ = VDD and L_ = GND.
The wiper terminal is unloaded and measured with a high-input-impedance voltmeter.
Note 3: R-DNL and R-INL are measured with the potentiometer configured as a variable resistor (Figure 1). DNL and INL are mea-
sured with the potentiometer configured as a variable resistor. H_ is unconnected and L_ = GND. For VDD = +5V, the wiper
terminal is driven with a source current of 400FA for the 10kI configuration, 80FA for the 50kI configuration, and 40FA for
the 100kI configuration. For VDD = +1.7V, the wiper terminal is driven with a source current of 150FA for the 10kI configu-
ration, 30FA for the 50kI configuration, and 15FA for the 100kI configuration.
Note 4: The wiper resistance is the worst value measured by injecting the currents given in Note 3 to W_ with L_ = GND.
RW_ = (VW_ - VH_)/IW_.
Note 5: Drive HA with a 1kHz GND to VDD amplitude tone. LA = LB = GND. No load. WB is at midscale with a 10pF load. Measure
WB.
Note 6: The wiper-settling time is the worst-case 0 to 50% rise time, measured between tap 0 and tap 127. H_ = VDD, L_ = GND,
and the wiper terminal is loaded with 10pF capacitance to ground.
Note 7: Digital timing is guaranteed by design and characterization, not production tested.
Note 8: The SCL clock period includes rise and fall times (tR = tF). All digital input signals are specified with tR = tF = 2ns and timed
from a voltage level of (VIL + VIH)/2.
Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. For I2C-bus specification infor-
mation from NXP Semiconductor (formerly Philips Semiconductor), refer to the UM10204: I2C-Bus Specification and User
Manual.
H
W
L
Figure 1. Voltage-Divider and Variable Resistor Configurations
N.C.
W
L
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