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MAX5035(2003) データシートの表示(PDF) - Maxim Integrated

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MAX5035 Datasheet PDF : 17 Pages
First Prev 11 12 13 14 15 16 17
1A, 76V, High-Efficiency MAXPower
Step-Down DC-DC Converter
Ensure that the ripple specification of the input capaci-
tor exceeds the worst-case capacitor RMS ripple cur-
rent. Use the following equations to calculate the input
capacitor RMS current:
where
ICRMS = IPRMS2 IAVGIN2
( ) IPRMS =
IPK2 + IDC2 +
IPK
×
IDC
×
D
3
IAVGIN
=
VOUT × IOUT
VIN × η
IPK
=
IOUT
+
IL
2
,
IDC =
IOUT
IL
2
and D = VOUT
VIN
IPRMS is the input switch RMS current, IAVGin is the
input average current, and η is the converter efficiency.
The ESR of aluminum electrolytic capacitors increases
significantly at cold temperatures. Use a 1µF or greater
value ceramic capacitor in parallel with the aluminum
electrolytic input capacitor, especially for input voltages
below 8V.
Output Filter Capacitor
The worst-case peak-to-peak and RMS capacitor ripple
current, allowable peak-to-peak output ripple voltage,
and the maximum deviation of the output voltage dur-
ing load steps determine the capacitance and the ESR
requirements for the output capacitors.
The output capacitance and its ESR form a zero, which
improves the closed-loop stability of the buck regulator.
Choose the output capacitor so the ESR zero frequency
(fZ) occurs between 20kHz to 40kHz. Use the following
equation to verify the value of fZ. Capacitors with 100m
to 250mESR are recommended to ensure the closed-
loop stability, while keeping the output ripple low.
fZ
=
2
×
π
×
1
COUT ×
ESROUT
The output ripple is comprised of VOQ (caused by the
capacitor discharge) and VOESR (caused by the ESR
of the capacitor). Use low-ESR tantalum or aluminum
electrolytic capacitors at the output. Assuming that the
contribution from the ESR and capacitor discharge
equal 80% and 20% respectively, calculate the output
capacitance and the ESR required for a specified rip-
ple using the following equations:
ESROUT
=
VOESR
IL
COUT
2.2 ×
IL
VOQ
× fSW
The MAX5035 has an internal soft-start time (tSS) of
400µs. It is important to keep the output rise time at
startup below tSS to avoid output overshoot. The output
rise time is directly proportional to the output capacitor.
Use 68µF or lower capacitance at the output to control
the overshoot below 5%.
In a dynamic load application, the allowable deviation
of the output voltage during the fast-transient load dic-
tates the output capacitance value and the ESR. The
output capacitors supply the step load current until the
controller responds with a greater duty cycle. The
response time (tRESPONSE) depends on the closed-
loop bandwidth of the converter. The resistive drop
across the capacitor ESR and capacitor discharge
cause a voltage droop during a step load. Use a com-
bination of low-ESR tantalum and ceramic capacitors
for better transient load and ripple/noise performance.
Keep the maximum output voltage deviation above the
tolerable limits of the electronics being powered.
Assuming a 50% contribution each from the output
capacitance discharge and the ESR drop, use the fol-
lowing equations to calculate the required ESR and
capacitance value:
ESROUT
=
VOESR
ISTEP
COUT
=
ISTEP
× tRESPONSE
VOQ
where ISTEP is the load step and tRESPONSE is the
response time of the controller. Controller response
time is approximately one-third of the reciprocal of the
closed-loop unity-gain bandwidth, 20kHz typically.
PC Board Layout Considerations
Proper PC board layout is essential. Minimize ground
noise by connecting the anode of the Schottky rectifier,
the input bypass capacitor ground lead, and the output
filter capacitor ground lead to a single point (star
______________________________________________________________________________________ 11

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