MAX5003 データシートの表示（PDF） - Maxim Integrated

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MAX5003

High-Voltage PWM Power-Supply Controller

Maxim Integrated 

High-Voltage PWM

Power-Supply Controller

Pin Description (continued)

PIN

NAME

FUNCTION

11

AGND

Analog Ground. Connect to PGND close to the IC.

Current Sense with Blanking. Turns power switch off if VCS rises above 100mV (referenced to PGND).

12

CS

Connect a 100Ω resistor between CS and the current-sense resistor (Figure 2). Connect CS to PGND if

not used.

13

PGND

Power Ground. Connect to AGND.

14

NDRV

Gate Drive for External N-Channel Power FET

Output Driver Power-Rail Decoupling Point. Connect a capacitor to PGND with half the value used for

15

VCC

VDD bypass very close to the pin. If synchronizing several controllers, power the fan-out buffer driving the

FREQ pins from this pin.

16

VDD

9.75V Internal Linear-Regulator Output. Drive VDD to a voltage higher than 10.75V to bootstrap the chip

supply. VDD is also the supply voltage rail for the chip. Bypass to AGND with a 5µF to 10µF capacitor.

Detailed Description

The MAX5003 is a PWM controller designed for use as

the control and regulation core of voltage-mode control

flyback converters or forward-voltage power convert-

ers. It provides the power-supply designer with maxi-

mum flexibility and ease of use. The device is specified

up to 110V and will operate from as low as 11V. Its

maximum operating frequency of 300kHz permits the

use of miniature magnetic components to minimize

board space. The range, polarity, and range of output

voltages and power are limited only by design and by

the external components used.

This device works in isolated and nonisolated configu-

rations, and in applications with single or multiple out-

put voltages. All the building blocks of a PWM

voltage-mode controller are present in the MAX5003

and its settings are adjustable. The functional diagram

is shown on Figure 1.

Modern Voltage-Mode Controllers

The MAX5003 offers a voltage-mode control topology

and adds features such as fast input voltage feed for-

ward, programmable maximum duty cycle, and high

operating frequencies. It has all the advantages of cur-

rent-mode control—good control loop bandwidth,

same-cycle response to input voltage changes, and

pulse-by-pulse current limiting. It eliminates disadvan-

tages such as the need for ramp compensation, noise

sensitivity, and the analytical and design difficulties of

dealing with two nested feedback loops. In summary,

voltage-mode control has inherent superior noise

immunity and uses simpler compensation schemes.

Internal Power Regulators

The MAX5003’s power stages operate over a wide

range of supply voltages while maintaining low power

consumption. For the high end of the range (+36V to

+110V), power is fed to the V+ pin into a depletion

junction FET preregulator. This input must be decou-

pled with a 0.1µF capacitor to the power ground pin

(PGND). To decouple the power line, other large-value

capacitors must be placed next to the power trans-

former connection.

The preregulator drops the input voltage to a level low

enough to feed a first low-dropout regulator (LDO)

(Figure 1). The input to the LDO is brought out at the ES

pin. ES must also be decoupled with a 0.1µF capacitor.

In applications where the maximum input voltage is

below 36V, connect ES and V+ together and decouple

with a 0.1µF capacitor.

The first LDO generates the power for the VDD line. The

VDD line is available at the VDD pin for decoupling. The

bypass to AGND must be a 5µF to 10µF capacitor.

When the maximum input voltage is always below

18.75V, power may also be supplied at VDD; in this

case, connect V+, ES, and VDD together.

Forcing voltages at VDD above 10.75V (see Electrical

Characteristics) disables the first LDO, typically reduc-

ing current consumption below 50µA (see Typical

Operating Characteristics).

Following the VDD LDO is another regulator that drives

VCC: the power bus for the internal logic, analog cir-

cuitry, and external power MOSFET driver. This regula-

tor is needed because the VDD voltage level would be

too high for the external N-channel MOSFET gate. The

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