MAX3786 データシートの表示（PDF） - Maxim Integrated

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MAX3786

1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization

Maxim Integrated 

1.5Gbps Serial ATA-Compatible Mux/Buffer with

Loopback and Equalization

PIN

1, 4, 8, 15,

17, 20, 21,

24, 26, 30

2

3

5

6

7

9

10

11

12

13

14

16, 25

18

19

22

23

27

28

29

31

32

EP

NAME

FUNCTION

Pin Description

VCC

+3.3V Supply Voltage

TX+

TX-

SEL

RX-

RX+

PE1EN

EQ1EN

LB_EN

CM1

IN1-

IN1+

GND

OUT1-

OUT1+

OUT0-

OUT0+

IN0-

IN0+

CM0

EQ0EN

PE0EN

Exposed

pad

Positive TX Data Output, CML. Serial ATA compatible.

Negative TX Data Output, CML. Serial ATA compatible.

Multiplex Select Control Input, LVCMOS. Set high to connect RX/TX to OUT1/IN1.

Negative RX Data Input, CML. Serial ATA compatible.

Positive RX Data Input, CML. Serial ATA compatible.

Channel 1 Preemphasis Enable Input, LVCMOS. Set low to enable OUT1 PE.

Channel 1 Equalization Enable Input, LVCMOS. Set low to enable IN1 EQ.

Loopback Enable Input, LVCMOS. Set low to loopback data on nonselected channel.

Input 1 Common-Mode Point. Normally not connected; can be connected to VCC through 1.0µF

capacitor. See Figure 1.

Negative Channel 1 Data Input, CML. Serial ATA compatible.

Positive Channel 1 Data Input, CML. Serial ATA compatible.

Supply Ground

Negative Channel 1 Data Output, CML. Serial ATA compatible.

Positive Channel 1 Data Output, CML. Serial ATA compatible.

Negative Channel 0 Data Output, CML. Serial ATA compatible.

Positive Channel 0 Data Output, CML. Serial ATA compatible.

Negative Channel 0 Data Input, CML. Serial ATA compatible.

Positive Channel 0 Data Input, CML. Serial ATA compatible.

Input 0 Common-Mode Point. Normally not connected; can be connected to VCC through 1.0µF

capacitor. See Figure 1.

Channel 0 Equalization Enable Input, LVCMOS. Set low to enable IN0 EQ.

Channel 0 Preemphasis Enable Input, LVCMOS. Set low to enable OUT0 PE.

Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and

electrical performance.

Detailed Description

The MAX3786 consists of three multiplexers, I/O buffers,

and LOS-detection circuitry (see the Functional Diagram).

The buffers on the controller side provide EQ on the

inputs and PE on the outputs.

Mux/Buffer Logic

By means of the LVCMOS input SEL, a SATA-compati-

ble device at TX/RX can be connected to either

IN0/OUT0 or IN1/OUT1. When SEL is low, TX/RX are

connected to IN0/OUT0, and when SEL is high, TX/RX

are connected to IN1/OUT1. Use of the SEL input pro-

vides the ability to operate a single SATA disk drive

from redundant controllers. Loopback is provided on

the IN_/OUT_ side and is controlled by the LVCMOS

input LB_EN. When LB_EN is low, the nonselected

IN_/OUT_ loops back (see Table 1). The SEL and

LB_EN control lines are internally pulled high through

40kΩ resistors (see the Functional Diagram).

Loss-of-Signal Logic

At each high-speed input to the MAX3786, an LOS cir-

cuit is provided. In this circuit, a differential signal of

50mVP-P or less is detected as OFF, and a signal of

greater than 150mVP-P is detected as ON. The LOS

detectors, in combination with the select logic, control

their associated high-speed output-disable circuits, so

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