MAX31865 データシートの表示（PDF） - Maxim Integrated

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MAX31865

RTD-to-Digital Converter

Maxim Integrated 

MAX31865

RTD-to-Digital Converter

3-Wire (D4)

Write 1 to this bit when using a 3-wire RTD connection.

In this mode the voltage between FORCE+ and RTDIN+

is subtracted from (RTDIN+ - RTDIN-) to compensate

for the IR errors caused by using a single wire for the

FORCE- and RTDIN- connections. When using 2-wire or

4-wire connections, write 0 to this bit.

Fault Detection Cycle (D3:D2)

The master initiated fault detection cycle has two modes

of operation, manual and automatic mode timing. If the

external RTD interface circuitry includes an input filter with

a time constant greater than 100Fs, the fault detection

cycle timing should be controlled in the manual mode

operation. The fault detection cycle checks for three

faults by making the following voltage comparisons and

setting the associated bits in the Fault Status Register:

1) Is the voltage at REFIN- greater than 85% x VBIAS?

(Fault Status Register bit D5)

2) Is the voltage at REFIN- less than 85% x VBIAS when

FORCE- input switch is open? (Fault Status Register

bit D4)

3) Is the voltage at RTDIN- less than 85% x VBIAS when

FORCE- input switch is open? (Fault Status Register

bit D3)

Note: All voltages are referenced to GND1.

The Applications Information provides tables for decoding

possible causes of set fault status bits.

To enter the automatic fault detection cycle, write

100X010Xb to the Configuration register. The ADC

is now in “Normally Off” mode. The automatic fault

detection cycle inserts 100Fs delays before checking for

faults, thereby allowing the external input filter to settle.

The Fault Detect Cycle bits (D[3:2]) self-clear to 00b

upon completion.

To enter the manual fault detection cycle, first ensure that

VBIAS has been on for at least 5 time constants. Next,

write 100X100Xb to the Configuration register. The ADC

is now in “Normally Off” mode. The MAX31865 checks

for faults while the FORCE- input switch is closed, and

when the check completes, the FORCE-input switch

opens. The Fault Detect Cycle bits (D[3:2]), remain set to

10b. Again, wait at least 5 time constants, and then write

100X110Xb to the Configuration register. The MAX31865

now checks for faults while the FORCE- inputs switch

is open; when the check completes, the FORCE- input

switch closes and the Fault Detect Cycle bits (D[3:2])

self-clear to 00b. Note that if 1 is written to D5 (1-Shot)

and D2 or D3 in a single write, both commands are

ignored. If 100X110Xb is set without a prior initiation of

the first manual step (setting 100X100Xb), the automatic

fault detection mode is run instead.

Fault Status Clear (D1)

Write a 1 to this bit while writing 0 to bits D5, D3, and D2

to return all fault status bits (D[7:2]) in the Fault Status

Register to 0. Note that bit D2 in the Fault Register, and

subsequently bit D0 in the RTD LSB register may be set

again immediately after resetting if an over/undervoltage

fault persists. The fault status clear bit D1, self-clears to

0.

50/60Hz (D0)

This bit selects the notch frequencies for the noise

rejection filter. Write 0 to this bit to reject 60Hz and

its harmonics; write 1 to this bit to reject 50Hz and its

harmonics. Note: Do not change the notch frequency

while in auto conversion mode.

Table 3. Fault-Detection Cycle Control Bits

D3 D2

00

01

10

CONFIGURATION REGISTER

WRITE (BINARY)

XXXX00XXb

100X010Xb

100X100Xb

11

X = Don’t care

100X110Xb

WRITE ACTION

READ MEANING

No action

Fault detection with automatic delay

Run fault detection with manual delay

(cycle 1)

Finish fault detection with manual delay

(cycle 2)

Fault detection finished

Automatic fault detection still running

Manual cycle 1 still running; waiting for

user to write 11

Manual cycle 2 still running

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