LH5P8128 データシートの表示（PDF） - Sharp Electronics
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LH5P8128 Datasheet PDF : 13 Pages
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LH5P8128
CMOS 1M (128K × 8) Pseudo-Static RAM
AC ELECTRICAL CHARACTERISTICS 1,2,3
(TA = 0 to +70°C, VCC = 5.0 V ±10%)
PARAMETER
SYMBOL
LH5P8128-60
MIN.
MAX.
LH5P8128-80
MIN. MAX.
LH5P8128-10
MIN. MAX.
UNIT
Random read, write cycle time
Read modify write cycle time
CE pulse width
CE precharge time
Address setup time
Address hold time
Read command setup time
Read command hold time
CE access time
OE access time
CE to output in Low-Z
OE to output in Low-Z
Output enable from end of write
Chip disable to output in High-Z
Output disable to output in High-Z
Write enable to output in High-Z
OE setup time
OE hold time
Write command pulse width
Write command setup time
Write command hold time
Data setup time from write
Data setup time from CE
Data hold time from write
Data hold time from CE
Transition time (rise and fall)
Refresh time interval
Refresh command hold time
Auto refresh cycle time
Refresh delay time from CE
Refresh pulse width
(Auto refresh)
Refresh precharge time
(Auto refresh)
Refresh pulse width (Self refresh)
CE delay time from refresh
precharge (Self refresh)
tRC
tRMW
tCE
tP
tAS
tAH
tRCS
tRCH
tCEA
tOEA
tCLZ
tOLZ
tWLZ
tCHZ
tOHZ
tWHZ
tOES
tOEH
tWP
tWCS
tWCH
tDSW
tDSC
tDHW
tDHC
tT
tREF
tRHC
tFC
tRFD
tFAP
tFP
tFAS
tFRS
100
130
160
ns
165
195
235
ns
60 10,000 80 10,000 100 10,000 ns
40
40
50
ns
0
0
0
ns
15
20
25
ns
0
0
0
ns
0
0
0
ns
60
80
100
ns
25
30
35
ns
20
20
20
ns
0
0
0
ns
0
0
0
ns
20
25
30
ns
20
25
30
ns
20
25
30
ns
0
0
0
ns
10
10
10
ns
30
30
30
ns
30
30
30
ns
40
50
60
ns
25
30
35
ns
25
30
35
ns
0
0
0
ns
0
0
0
ns
3
35
3
35
3
35
ns
8
8
8
ms
15
15
15
ns
100
130
160
ns
30
40
50
ns
30 8,000 30 8,000 30 8,000 ns
30
30
30
ns
8,000
8,000
8,000
ns
140
160
190
ns
NOTES:
1. In order to initialize the circuit, CE1 should be kept at VIH or CE2
should be kept at VIL for 100 µs after power-up, followed by at
least 8 dummy cycles.
2. AC characteristics are measured at t T = 5 ns.
3. AC characteristics are measured at the following condition (see
figure at right).
4. Address is latched at the negative edge of CE1 or at the positive
edge of CE2.
5. Measured with a load equivalent to 2TTL + 100 pF.
6. Data is latched at the positive edge of W/R or at the positive
edge of CE1 or at the negative edge of CE2.
INPUT
OUTPUT
2.4 V
0.8 V
2.2 V
0.8 V
Figure 4. AC Characteristics
NOTE
4
4
5
5
6
6
6
6
2.6 V
0.6 V
5P8128-3
4
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