KK82C55A
GROUP
A
CONTROL
D7-D0
DATA
BUS
BUFFER
8 BIT
INTERNAL
DATA BUS
GROUP
A
PORT
A
(8)
GROUP
A
PORT C
UPPER
(4)
GROUP
B
PORT C
LOWER
(4)
PA7-PA0
PC7-PC4
PC3-PC0
RD
WR
A1
A0
Reset
CS
READ/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
GROUP
B
PORT
B
(8)
PB7-PB0
Figure 3.KK82C55AN Block Diagram Showing Data Bus Buffer and Read Write Control Logic Functions
*
RESET
INTERNAL
DATA IN
INTERNAL
DATA OUT
RESET
DIENAXPTTTOEPAERRIRNNOTNAUAALTL
WR
VCC
P*
EXTERNAL
PORT B,C
PIN
INTERNAL
DATA OUT
WR
*NOTE:
Port pins loaded with more than 20pF capacitance may not have their logic level guaranteed following a hardware reset.
Figure 4. Port A, B, C, Bus-hold Configuration
4