IS61LP6432A データシートの表示（PDF） - Integrated Silicon Solution

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IS61LP6432A

64K x 32, 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM

Integrated Silicon Solution 

IS61LP6432A

IS61LP6436A

INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)

External Address

A1 A0

00

01

10

11

1st Burst Address

A1 A0

01

00

11

10

2nd Burst Address

A1 A0

10

11

00

01

3rd Burst Address

A1 A0

11

10

01

00

ISSI ®

LINEAR BURST ADDRESS TABLE (MODE = Vss)

0,0

A1', A0' = 1,1

0,1

1,0

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameter

TSTG

Storage Temperature

PD

Power Dissipation

IOUT

Output Current (per I/O)

VIN, VOUT Voltage Relative to Vss for I/O Pins

VIN

Voltage Relative to Vss for

for Address and Control Inputs

VDD

Voltage on VDD Supply Relative to Vss

Value

Unit

–55 to +150

°C

1.6

W

100

mA

–0.5 to VDDQ + 0.3 V

–0.5 to VDD + 0.5 V

–0.5 to 4.6

V

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-

nent damage to the device. This is a stress rating only and functional operation of the device

at these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2. This device contains circuitry to protect the inputs against damage due to high static voltages

or electric fields; however, precautions may be taken to avoid application of any voltage higher

than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

09/02/05

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