IDT54FCT810BTLB データシートの表示（PDF） - Integrated Device Technology
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IDT54FCT810BTLB Datasheet PDF : 6 Pages
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IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR ALL OUTPUTS
VCC
7.0V
VIN
Pulse
Generator
V OUT
D.U.T.
500Ω
50pF
500Ω
RT
CL
3103 drw 04
ENABLE AND DISABLE TIME
SWITCH POSITION
Test
Switch
Disable LOW
Closed
Enable LOW
Disable HIGH
Open
Enable HIGH
DEFINITIONS:
3103 lnk 07
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
TEST WAVEFORMS
PACKAGE DELAY
INPUT
tPLH
OUTPUT
3V
1.5V
0V
tPHL
VOH
2.0V
1.5V
0.8V VOL
tR
tF
3103 drw 05
OUTPUT SKEW (ALL BANKS) - tSK2(o)
OUTPUT SKEW (SAME BANK) - tSK1(o)
3V
INPUT
tPLH1
tPHL1
1.5V
0V
VOH
OUTPUT 1
tSK1(o)
tSK1(o)
1.5V
VOL
VOH
OUTPUT 2
tPLH2
tPHL2
1.5V
VOL
tSK1(o) = |tPLH2 - tPLH1| or |tPHL2 - tPLH1|
3103 drw 06
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK2(o)
tSK2(o)
tPHL2
tPLH2
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
PULSE SKEW - tSK(p)
INPUT
OUTPUT
tPLH
tPHL
tSK(p) = |tPHL - tPLH|
3V
1.5V
0V
VOH
1.5V
VOL
tSK2(o) = |tPHL2 - tPLH1| or |tPLH2 - tPHL1| 3103 drw 07
3103 drw 08
PACKAGE SKEW - tSK(t)
ENABLE AND DISABLE TIMES
INPUT
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
tPD1a
tPD1b
tSK2(o)
tSK2(o)
tPD2a
tPD2b
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
tSK(t) = |tPD2a - tPD1a| or |tPD2b- tPD1b|
Package 1 and Package 2 are same device type and speed grade
NOTES:
3103 drw 09
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
t PZL
SWITCH
CLOSED
t PZH
SWITCH
OPEN
DISABLE
3.5V
1.5V
t PHZ
t PLZ
0.3V
1.5V
0V
0.3V
3V
1.5V
0V
3.5V
VOL
VOH
0V
3103 drw 10
9.4
5
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