ICS9250-27 データシートの表示（PDF） - Integrated Device Technology
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ICS9250-27
Integrated Device Technology
ICS9250-27 Datasheet PDF : 15 Pages
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ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
General Description
The ICS9250-27 is a single chip clock solution for 810/810E and 815 type chipset. It provides all necessary clock
signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10
dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-
27 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Pin Description
PIN NUMBER PIN NAME
FS2
1
REF0
3
X1
4
X2
5, 6, 14, 17, 23,
24, 35, 41, 47, GND
48, 56
9, 8, 7
3V66 (2:0)
2, 10, 11, 21,
22, 27, 33, 38, VDD
44
12
PCICLK_F
20, 19, 18, 16,
15, 13
PCICLK (5:0)
25
48MHz_0
26
48MHz_1
29, 28
FS (1:0)
30
SDATA
TYPE
DESCRIPTION
IN Function Select pin. Determines CPU frequency, all output functionality
OUT 3.3V, 14.318MHz reference clock output.
IN
OUT
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
PWR Ground pins for 3.3V supply
OUT 3.3V Fixed 66MHz clock outputs for HUB
PWR 3.3V power supply
OUT Free running 3.3V PCI clock output
OUT 3.3V PCI clock outputs
OUT
OUT
IN
I/O
3.3V Fixed 48MHz clock outputs for USB
3.3V fixed 48MHz clock output. Stronger output for graphics/video
interface (minimum 1V/ns edge rate)
Function Select pins. Determines CPU frequency, all output
functionality. Please refer to Functionality table on page 1
Data pin for I2C circuitry 5V tolerant
31
SCLK
32
PD#
36, 37, 39, 40,
42, 43, 45, 46
SDRAM (7:0)
34
SDRAM_F
49, 50, 52
CPUCLK
(2:0)
51, 53
VDDL
IN Clock pin of I2C circuitry 5V tolerant
IN
OUT
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the VCO
and the crystal are stopped. The latency of the power down will not
be greater than 3ms.
3.3V output running 100MHz. All SDRAM outputs can be turned off
through I2C
OUT 3.3V free running 100MHz SDRAM, cannot be turned off through I2C
OUT
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS pins.
PWR 2.5V power suypply for CPU & IOAPIC
54, 55
IOAPIC (1:0) OUT 2.5V clock outputs running at 33.3MHz.
IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
2
0395F—01/25/10
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