EP9307-IRZ データシートの表示（PDF） - Cirrus Logic

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EP9307-IRZ

ARM9 SOC with Ethernet, USB, Display, and Touchscreen

Cirrus Logic 

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Real-Time Clock with Software Trim

The software trim feature on the real time clock (RTC)

provides software controlled digital compensation of the

32.768 KHz input clock. This compensation is accurate to

±1.24 sec/month.

Note: A real time clock must be connected to RTCXTALI or

the EP9307 device will not boot.

Table K. Real-Time Clock with Pin Assignments

Pin Mnemonic

Pin Name - Description

RTCXTALI

RTCXTALO

Real-Time Clock Oscillator Input

Real-Time Clock Oscillator Output

PLL and Clocking

The Processor and the Peripheral Clocks operate from a

single 14.7456 MHz crystal.

The Real Time Clock operates from a 32.768 KHz

external oscillator.

Table L. PLL and Clocking Pin Assignments

Pin Mnemonic

XTALI

XTALO

VDD_PLL

GND_PLL

Pin Name - Description

Main Oscillator Input

Main Oscillator Output

Main Oscillator Power

Main Oscillator Ground

Timers

The Watchdog Timer ensures proper operation by

requiring periodic attention to prevent a reset-on-time-

out.

Two 16-bit timers operate as free running down-counters

or as periodic timers for fixed interval interrupts and have

a range of 0.03 ms to 4.27 seconds.

One 32-bit timer, plus a 6-bit prescale counter, has a

range of 0.03 μs to 73.3 hours.

One 40-bit debug timer, plus a 6-bit prescale counter, has

a range of 1.0 μs to 12.7 days.

Interrupt Controller

The interrupt controller allows up to 62 interrupts to

generate an Interrupt Request (IRQ) or Fast Interrupt

Request (FIQ) signal to the processor core. Thirty-two

hardware priority assignments are provided for assisting

IRQ vectoring, and two levels are provided for FIQ

vectoring. This allows time critical interrupts to be

processed in the shortest time possible. Internal

interrupts may be programmed as active high or active

low level sensitive inputs. GPIO pins programmed as

interrupts may be programmed as active high level

sensitive, active low level sensitive, rising edge triggered,

falling edge triggered, or combined rising/falling edge

triggered.

• Supports 64 interrupts from a variety of sources (such

as UARTs, GPIO, and key matrix)

• Routes interrupt sources to either the ARM920T’s

IRQ or FIQ (Fast IRQ) inputs

• Three dedicated off-chip interrupt lines operate as

active high level sensitive interrupts

• Any of the 16 GPIO lines maybe configured to

generate interrupts

• Software supported priority mask for all FIQs and

IRQs

Table M. External Interrupt Controller Pin Assignment

Pin Mnemonic

Pin Name - Description

INT[2:0]

External Interrupts 2, 1, 0

Dual LED Drivers

Two pins are assigned specifically to drive external

LEDs.

Table N. Dual LED Pin Assignments

Pin Mnemonic

Pin Name -

Description

Alternative Usage

GRLED

REDLED

Green LED

Red LED

General Purpose I/O

General Purpose I/O

General Purpose Input/Output (GPIO)

The 14 EGPIO pins may each be configured individually

as an output, an input, or an interrupt input.

There are 22 pins that may alternatively be used as input,

output, or open-drain pins, but do not support interrupts.

These pins are:

• Key Matrix ROW[7:0], COL[7:0]

• Ethernet MDIO

• Both LED Outputs

• Two-wire Clock and Data

• GGPIO[2]

• HGPIO[7:2]

6 pins may alternatively be used as inputs only:

• CTSn, DSRn/DCDn

• 4 Interrupt Lines

2 pins may alternatively be used as outputs only:

• RTSn

• ARSTn

10

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