DM9102A データシートの表示（PDF） - Unspecified
部品番号
コンポーネント説明
一致するリスト
DM9102A Datasheet PDF : 77 Pages
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Bit
Default
31:7 Undefined
6:1
000000
0
1
DM9102A
Single Chip Fast Ethernet NIC controller
Type
RW
RO
RO
Description
PCI I/O Base Address
This is the base address value for I/O accesses cycles. It will be compared to
AD[31:7] in the address phase of bus command cycle for the I/O resource access.
PCI I/O Range Indication
It indicates that the minimum I/O resource size is 80h.
I/O Space Or Memory Space Base Indicator
Determines that the register maps into the I/O space.( = 1 Indicates I/O Base)
Memory Mapped Base Address (xxxxxx14 - PCIMEM)
31
Memory Mapped
Base
Memory Base Address
Memory Range Indication
I/O or Memory Space Indicator
87
10
0000000
0
Bit
Default
31:7 Undefined
6:1
000000
0
0
Type
R/W
RO
RO
Description
PCI Memory Base Address
This is the base address value for Memory accesses cycles. It will be compared to
the AD[31:7] in the address phase of bus command cycle for the Memory resource
access.
PCI Memory Range Indication
It indicates that the minimum Memory resource size is 80h.
I/O Space Or Memory Space Base Indicator
Determines that the register maps into the memory space( = 0 Indicates Memory
Base)
Subsystem Identification (xxxxxx2c - PCISID)
31
Subsystem ID
Subsystem ID
Subsystem Vendor ID
0
Subsystem Vendor ID
Bit
31:16
15:0
Default
XXXXh
XXXXh
Type
RO
RO
Description
Subsystem ID
It can be loaded from EEPROM word 1 and different from each card.
Subsystem Vendor ID
Unique number given by PCI SIG and loaded from EEPROM word 0.
Final
19
Version: DM9102A-DS-F03
August 28, 2000
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