7C1021-12 データシートの表示（PDF） - Cypress Semiconductor
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7C1021-12 Datasheet PDF : 9 Pages
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CY7C1021
AC Test Loads and Waveforms
R 481Ω
5V
R 481Ω
5V
OUTPUT
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
Equivalent to: THÉVENIN OUTPUT
EQUIVALENT
167
30 pF
R2
255Ω
1021-3
1.73V
3.0V
GND
< 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
< 3 ns
1021-4
Switching Characteristics[5] Over the Operating Range
7C1021-10 7C1021-12 7C1021-15 7C1021-20
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
WRITE CYCLE[8]
10
12
15
20
ns
10
12
15
20 ns
3
3
3
3
ns
10
12
15
20 ns
5
6
7
9
ns
0
0
0
0
ns
5
6
7
9
ns
3
3
3
3
ns
5
6
7
9
ns
0
0
0
0
ns
10
12
15
20 ns
5
6
7
9
ns
0
0
0
0
ns
5
6
7
9
ns
tWC
Write Cycle Time
10
12
15
20
ns
tSCE
CE LOW to Write End
8
9
10
12
ns
tAW
Address Set-Up to Write End
7
8
10
12
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
12
ns
tSD
Data Set-Up to Write End
5
6
8
10
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[6, 7]
0
0
0
0
ns
3
3
3
3
ns
5
6
7
9
ns
tBW
Byte Enable to End of Write
7
8
9
12
ns
Shaded areas contain preliminary information.
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05054 Rev. **
Page 3 of 9
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