CS8403A データシートの表示（PDF） - Cirrus Logic
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CS8403A Datasheet PDF : 33 Pages
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CS8403A CS8404A
SWITCHING CHARACTERISTICS - SERIAL PORTS
(TA = 25 °C; VD+ = 5V; Inputs: Logic0 = GND, Logic1 = VD+; CL = 20 pF)
Input Word Rate
SCK Frequency
Parameters
Master Mode
Slave Mode
Note 5
Note 6
Note 6
SCK Pulse Width Low
Slave Mode
Note 6
SCK Pulse Width High
Slave Mode
Note 6
SCK rising to FSYNC edge delay
Notes 6, 7
SCK rising to FSYNC edge setup
Notes 6, 7
SDATA valid to SCK rising setup
Note 7
SCK rising to SDATA hold time
Note 7
C, U, V valid to SCK rising setup
SCK rising to C, U, V hold time
CS8404A
non-CD Mode Notes 7, 8
CS8404A
non-CD Mode Notes 7, 8
U valid to SBC rising setup
Note 8
CS8404A, CD mode
SBC rising to U hold time
Note 8
CS8404A, CD mode
Symbol
IWR
tsckf
tsckl
tsckh
tsfds
tsfs
tsss
tssh
tcss
tscs
tuss
tsuh
Min
Typ
Max Units
-
-
108 kHz
- IWR x 64 -
Hz
-
12.5 MHz
25
-
-
ns
25
-
-
ns
20
-
-
ns
20
-
-
ns
20
-
-
ns
20
-
-
ns
0
-
-
ns
50
-
-
ns
0
-
-
ns
80
-
-
ns
RST Pulse Width
CS8404A
150
-
-
ns
Notes: 5. The input word rate (IWR) refers to the frequency at which stereo audio input sample pairs are input to
the part. (A stereo pair is two audio samples.) Therefore, in Master mode, there are always 32 SCK
periods in one audio sample.
6. Master mode is defined as SCK and FSYNC being outputs. In Slave mode they are inputs. In the
CS8403A, control register 3 bit 1, MSTR, selects master. In the CS8404A, only format 0 is master.
7. The table above assumes data is output on the falling edge and latched on the rising edge. In both parts
the edge is selectable. The table is defined for the CS8403A with control register 3 bit 0, SCED, set to
one, and for the CS8404A in formats 4 through 7. For the other formats, the table and figure edges must
be reversed (i.e. “rising” to “falling” and vice versa).
8. The diagrams show SBC rising coincident with the first rising edge of SCK after FSYNC transitions.
This is true for all modes except FSF0 & 1 both equal 1 in the CS8403A, and format 4 in the CS8404A.
In these modes SBC is delayed one full SCK period.
FSYNC
t sfds
t sfs
t sckl t sckh
SCK
SDATA
t sss
t ssh
Serial Input Timing - Slave Mode
DS239PP1
5
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