CS61318-IP データシートの表示（PDF） - Cirrus Logic

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CS61318-IP

E1 Line Interface Unit

Cirrus Logic 

CS61318

RCLK

LATN

1

2

3

4

5

LATN = 1 RCLK, 9.5 dB of Attenuation

LATN = 2 RCLK, 1 9.5 dB of Attenuation

LATN = 3 RCLK, 28.5 dB of Attenuation

LATN = 4 RCLK, 0 dB of Attenuation

Figure 7. LATN Pulse Width encoding

0

Minimum Attenuation Limit

10

20

30

40

50

CS61318

60

Measured Performance

1

10

100

1k

10 k

Frequency in Hz

Figure 8. Typical Jitter Transfer Function

paths, or it can be eliminated from the circuit by

setting the XTALIN, pin 9, high. The jitter attenu-

ator on the CS61318 does not require a crystal, and

can be activated by setting XTALIN, pin 9, low

(preferred) or by floating pin 9.

The jitter attenuator’s corner frequency is approxi-

mately 1.25 Hz in order to comply with ETSI 300

011, CTR12, and recommendation I.431. A typical

jitter attenuation graph is shown in Figure 8.

2.6 Receiver Loss of Signal

The receiver will indicate loss of signal by setting

LOS, pin 12 high (CR1.0 = 1 in host mode), upon

power up, reset, when receiver gain is maximized,

or upon receiving 175+/-15 consecutive zeros. Re-

ceived zeros are counted based on recovered clock

cycles. When in the LOS state, received data is not

output from RPOS/RNEG (RDATA); but is

squelched until the device comes out of LOS. The

LOS condition is exited using ITU-T G.775 crite-

ria, namely 12.5% ones density for 175+/-75 bit pe-

riods with no more than 100 consecutive zeros. The

receiver recovers signals down to -36 dB, and LOS

will be declared below this signal level.

In LOS, the RCLK frequency depends on whether

MCLK is applied, and whether the jitter attenuator

is in the transmit or receive path. If the jitter atten-

uator is in the receive path, the jitter attenuator will

hold over the average incoming data frequency pri-

or to LOS. RPOS (RDATA) and RNEG pins are

forced low upon LOS.

When the jitter attenuator is in the transmit path or

not used, the clock recovery is referenced to

MCLK, if provided, or the crystal oscillator. The

frequency of RCLK in this case will simply remain

slaved to the clock reference upon loss of data. The

recovered clock remains as a 50% duty cycle clock.

2.7 Local Loopback

Local loopback is selected by setting LLOOP, pin

27, high (CR1.6 = 1 in host mode). Selecting local

loopback causes clock and data presented on

TCLK, TPOS/TNEG (TDATA) to be output at

RCLK, RPOS/RNEG (RDATA). Inputs to the

transmitter are still transmitted on TTIP and

10

DS441PP2

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