CS61884 データシートの表示（PDF） - Cirrus Logic

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CS61884

Octal T1/E1/J1 Line Interface Unit

Cirrus Logic 

CS61884

The CS61884 also allows the user to customize the

transmit pulse shapes to compensate for non-stan-

dard cables, transformers, or protection circuitry.

For further information on the AWG Refer to Ar-

bitrary Waveform Generator (See Section 15 on

page 43).

For more information on the host mode registers,

refer to Register Descriptions (See Section 14 on

page 35).

9.3 RZ Mode

In RZ mode, the internal pulse shape circuitry is

bypassed and RZ data driven into TPOS/TNEG is

transmitted on TTIP/TRING. In this mode, the

pulse width of the transmitter output is determined

by the width of the RZ signal input to

TPOS/TNEG. This mode is entered when MCLK

does not exist and TCLK is held “High” for at least

12 µsec.

9.1 Bipolar Mode

Bipolar mode provides transparent operation for

applications in which the line coding function is

performed by an external framing device. In this

mode, the falling edge of TCLK samples NRZ data

on TPOS/TNEG for transmission on TTIP/TRING.

9.2 Unipolar Mode

In unipolar mode, the CS61884 is configured such

that transmit data is encoded using B8ZS, HDB3,

or AMI line codes. This mode is activated by hold-

ing TNEG/UBS “High” for more than 16 TCLK

cycles. Transmit data is input to the part via the

TPOS/TDATA pin on the falling edge of TCLK.

When operating the part in hardware mode, the

CODEN pin is used to select between B8ZS/HDB3

or AMI encoding. During host mode operation, the

line coding is selected via the Global Control Reg-

ister (0Fh) (See Section 14.16 on page 38).

NOTE: The encoders/decoders are selected for all

eight channels in both hardware and host

mode.

9.4 Transmitter Powerdown / High-Z

The transmitters can be forced into a high imped-

ance, low power state by holding TCLK of the ap-

propriate channel low for at least 12µs or 140

MCLK cycles. In hardware and host mode, the

TXOE pin forces all eight transmitters into a high

impedance state within 1µs.

In host mode, each transmitter is individually con-

trollable using the Output Disable Register (12h)

(See Section 14.19 on page 39). The TXOE pin can

be used in host mode, but does not effect the con-

tents of the Output Enable Register. This feature is

useful in applications that require redundancy.

9.5 Transmit All Ones (TAOS)

When TAOS is activated, continuous ones are

transmitted on TTIP/TRING using MCLK as the

transmit timing reference. In this mode, the TPOS

and TNEG inputs are ignored.

In hardware mode, TAOS is activated by pulling

TCLK “High” for more than 16 MCLK cycles.

LEN[2:0]

000

001

010

011

100

101

110

111

Table 5. Hardware Mode Line Length Configuration Selection

Transmit Pulse Configuration

E1 3.0V / E1 2.37V

DS1, Option A (undershoot)

DS1, Option A (0 dB)

DSX-1: 0-133 ft. (0.6dB)

DSX-1: 133-266 ft. (1.2dB)

DSX-1: 266-399 ft. (1.8dB)

DSX-1: 399-533 ft. (2.4dB)

DSX-1: 533-655 ft. (3.0dB)

Line Z

120Ω / 75Ω

100Ω

100Ω

100Ω

100Ω

100Ω

100Ω

100Ω

Operation

E1

T1/J1

T1/J1

T1/J1

T1/J1

T1/J1

T1/J1

T1/J1

DS485PP4

25

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