CS61884 データシートの表示（PDF） - Cirrus Logic
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CS61884 Datasheet PDF : 72 Pages
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CS61884
3.4 Cable Select
SYMBOL
CBLSEL
LQFP FBGA TYPE
DESCRIPTION
Cable Impedance Select
Host Mode - The input voltage to this pin does not effect
normal operation.
Hardware Mode - This pin is used in combination with the
LEN control pins (Refer to Table 5, “Hardware Mode Line
Length Configuration Selection,” on page 25) to set the line
impedance for all eight receivers and transmitters. This pin
also selects whether or not all eight receivers use an inter-
nal or external line matching network (Refer to the Table
below for proper settings).
93
G13
I
Table 3. Cable Impedance Selection
E1/T1/J1
T1/J1
T1/J1
T1/J1
E1
E1
E1
CBLSEL
No Connect
HIGH
LOW
No Connect
HIGH
LOW
Transmitters
100 Ω Internal
100 Ω Internal
100 Ω Internal
120 Ω Internal
75 Ω Internal
75 Ω Internal
Receivers
Internal
Internal
External
Inter or Ext
Internal
External
3.5 Status
NOTE: Refer to Figure 17 on page 51 and Figure 18 on
page 52 for appropriate external line matching com-
ponents. All transmitters use internal matching net-
works.
SYMBOL
LOS0
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
LQFP FBGA TYPE
DESCRIPTION
42
K4
35
K3
75
K12
68
K11
113 E11
106 E12
3
E3
140
E4
O Loss of Signal Output
O
O The LOS output pins can be configured to indicate a loss of
O signal (LOS) state that is compliant to either T1.231, ITU
O G.775 or ETSI 300 233. These pins are asserted “High” to
O indicate LOS. The LOS output returns low when an input
O signal is present for the time period dictated by the associ-
O ated specification (Refer to Loss-of-Signal (LOS) (See
Section 10.5 on page 27)).
DS485PP4
15
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