CS5421 データシートの表示（PDF） - ON Semiconductor

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CS5421

Dual Out−of−Phase Synchronous Buck Controller with Remote Sense

ON Semiconductor 

CS5421

PSWH(OFF) = upper MOSFET switch−off losses;

VIN = input voltage;

IOUT = load current;

tRISE = MOSFET rise time (from FET manufacturer’s

switching characteristics performance curve);

tFALL = MOSFET fall time (from FET manufacturer’s

switching characteristics performance curve);

T = 1/fSW = period.

The total power dissipation in the switching MOSFET can

then be calculated as:

PHFET(TOTAL) + PRMS(H) ) PSWH(ON) ) PSWH(OFF)

where:

PHFET(TOTAL) = total switching (upper) MOSFET losses;

PRMS(H) = upper MOSFET switch conduction Losses;

PSWH(ON) = upper MOSFET switch−on losses;

PSWH(OFF) = upper MOSFET switch−off losses;

Once the total power dissipation in the switching FET is

known, the maximum FET switch junction temperature can

be calculated:

TJ + TA ) [PHFET(TOTAL) RQJA]

where:

TJ = FET junction temperature;

TA = ambient temperature;

PHFET(TOTAL) = total switching (upper) FET losses;

RΘJA = upper FET junction−to−ambient thermal resistance.

Selection of the Synchronous (Lower) FET

The switch conduction losses for the lower FET can be

calculated as follows:

PRMS(L) + IRMS2 RDS(ON)

+ [IOUT Ǹ(1.0 * D)]2 RDS(ON)

where:

PRMS(L) = lower MOSFET conduction losses;

IOUT = load current;

D = Duty Cycle;

RDS(ON) = lower FET drain−to−source on−resistance.

The synchronous MOSFET has no switching losses,

except for losses in the internal body diode, because it turns

on into near zero voltage conditions. The MOSFET body

diode will conduct during the non−overlap time and the

resulting power dissipation (neglecting reverse recovery

losses) can be calculated as follows:

PSWL + VSD ILOAD non−overlap time fSW

where:

PSWL = lower FET switching losses;

VSD = lower FET source−to−drain voltage;

ILOAD = load current;

Non−overlap time = GATE(L)−to−GATE(H) or

GATE(H)−to−GATE(L) delay (from CS5421 data sheet

Electrical Characteristics section);

fSW = switching frequency.

The total power dissipation in the synchronous (lower)

MOSFET can then be calculated as:

PLFET(TOTAL) + PRMS(L) ) PSWL

where:

PLFET(TOTAL) = Synchronous (lower) FET total losses;

PRMS(L) = Switch Conduction Losses;

PSWL = Switching losses.

Once the total power dissipation in the synchronous FET

is known the maximum FET switch junction temperature

can be calculated:

TJ + TA ) [PLFET(TOTAL) RQJA]

where:

TJ = MOSFET junction temperature;

TA = ambient temperature;

PLFET(TOTAL) = total synchronous (lower) FET losses;

RΘJA = lower FET junction−to−ambient thermal resistance.

Control IC Power Dissipation

The power dissipation of the IC varies with the MOSFETs

used, VCC, and the CS5421 operating frequency. The

average MOSFET gate charge current typically dominates

the control IC power dissipation.

The IC power dissipation is determined by the formula:

PCONTROL(IC) + ICC1VCC1 ) PGATE(H)1

) PGATE(L)1 ) PGATE(H)2 ) PGATE(L)2

where:

PCONTROL(IC) = control IC power dissipation;

ICC1 = IC quiescent supply current;

VCC1 = IC supply voltage;

PGATE(H) = upper MOSFET gate driver (IC) losses;

PGATE(L) = lower MOSFET gate driver (IC) losses.

The upper (switching) MOSFET gate driver (IC) losses

are:

PGATE(H) + QGATE(H) fSW VCC

where:

PGATE(H) = upper MOSFET gate driver (IC) losses;

QGATE(H) = total upper MOSFET gate charge at VCC;

fSW = switching frequency;

The lower (synchronous) MOSFET gate driver (IC)

losses are:

PGATE(L) + QGATE(L) fSW VGATE(L)

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