CS44L10-KZ データシートの表示（PDF） - Cirrus Logic
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CS44L10-KZ Datasheet PDF : 34 Pages
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CS44L10
4.9.3 DOUBLE SPEED MODE (DBS)
Default = 0
0 - Single Speed
1 - Double Speed (DBS)
Function:
Single Speed supports 8kHz to 50 kHz sample rates and Double Speed supports 50 kHz to 96kHz sample
rates. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer
to Tables 11, 12, 13, 14, and Section 6.2.
Note: De-emphasis, ramp control, and treble control are not available in Double Speed Mode.
4.9.4 FREQUENCY SHIFT (FRQSFT)
Default = 00
Function:
MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to
Tables 11, 12, 13, 14, and Section 6.2.
LRCK
(kHz)
48
48
48
44.1
44.1
44.1
32
32
32
24
24
24
12
12
12
8
8
8
DBS = 0
MCLKDIV = 0
MCLK/
LRCK
MCLK
(MHz)
DBS = 0
MCLKDIV = 1
MCLK/
LRCK
MCLK
(MHz)
PWM
Switching
FRQSFT1 FRQSFT0 CLKDIV1 CLKDIV0 Freq. (kHz)
256
12.288
512
24.576
0
0
0
0
384
18.432
768
36.864
0
0
0
1
384
512
24.576
1024
49.152
0
0
1
0
256
11.2896
512
22.5792
0
0
0
0
384
16.9344
768
33.8688
0
0
0
1
352.8
512
22.5792
1024
45.1584
0
0
1
0
512
16.384
1024
32.768
0
1
0
0
768
24.576
1536
49.152
0
1
0
1
512
1024
32.768
2048
65.536
0
1
1
0
512
12.288
1024
24.576
0
1
0
0
768
18.432
1536
36.864
0
1
0
1
384
1024
24.576
2048
49.152
0
1
1
0
1024
12.288
2048
24.576
1
0
0
0
1536
18.432
3072
36.864
1
0
0
1
384
2048
24.576
4096
49.152
1
0
1
0
1536
12.288
3072
24.576
1
1
0
0
2304
18.432
4608
36.864
1
1
0
1
384
3072
24.576
6144
49.152
1
1
1
0
Table 11. Single Speed Clock Modes - Control Port Mode
DS541PP1
21
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