CS44L10 データシートの表示（PDF） - Cirrus Logic

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CS44L10

Digital PWM Headphone Monitor

Cirrus Logic 

CS44L10

Left Channel

Audio Data

Channel A

Digital

Volume

EQ

Control

& Mute

Σ

HP_A

Right Channel

Audio Data

Channel B

Digital

Volume

Control

EQ

& Mute

Figure 5. Dynamics Control Block Diagram

HP_B

4.9 Mode Control 2 (address 0Ah)

7

MCLKDIV

0

6

CLKDV1

0

5

CLKDV0

0

4

DBS

0

3

FRQSFT1

0

2

FRQSFT0

0

1

DEM1

0

0

DEM0

0

4.9.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

Default = 0

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other

internal circuitry. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK require-

ments. Refer to Tables 11, 12, 13, 14, and Section 6.2.

4.9.2 CLOCK DIVIDE (CLKDIV)

Default = 00

Function:

MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to

Tables 11, 12, 13, 14, and Section 6.2.

20

DS541PP1

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