CS5333 データシートの表示（PDF） - Cirrus Logic

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CS5333

24-Bit, 96 kHz Stereo A/D Converter

Cirrus Logic 

CS5333

4. APPLICATIONS

4.1 Grounding and Power Supply

Decoupling

As with any high resolution converter, the CS5333

requires careful attention to power supply and

grounding arrangements to optimize performance.

Figure 3 show the recommended power arrange-

ment with VA and VL connected to clean supplies.

Decoupling capacitors should be located as close to

the device package as possible.

4.2 Oversampling Modes

The CS5333 operates in one of two oversampling

modes. Base Rate Mode supports input sample

rates up to 50 kHz while High Rate Mode supports

input sample rates up to 100 kHz. See Table 1 for

more details.

4.3 Recommended Power-up Sequence

1) Hold RST low until the power supply, master,

and left/right clocks are stable. In this state, VQ

will remain low.

2) Bring RST high. The device will remain in a

low power state with VQ low and will initiate

the power-up sequence. This power-up se-

quence takes approximately 1024 LRCK cycles

to complete.

4.4 Master/Slave Mode

In Master, Base Rate Mode (Pull-up on SDATA,

DIV=0), the CS5333 requires a 256x MCLK and

provide a 64x SCLK. In Master, High Rate Mode

(Pull-up on SDATA, DIV=1), the CS5333 requires

a 128x MCLK and provide a 64x SCLK. The vari-

ous clocking ratios required in Slave Mode (Pull-

down on SDATA) are listed under the description

of MCLK, on page 11.

DS520PP1

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