ACS101A データシートの表示（PDF） - Semtech Corporation
部品番号
コンポーネント説明
一致するリスト
ACS101A Datasheet PDF : 12 Pages
| |||
For asynchronous operation, the choice of clock frequency
dictates the sample rate of the asynchronous data appearing at
the input TxD, and consequently the jitter on the output RxD. The
sample frequency is always 1/36 of the chosen clock frequency in
'standard' mode and 1/72 in 'double' mode.
enables the system designer to use the ACS101A for the
transmission of packets of data with blank periods between
packets. The minimum quanta of data that can be sent over the
link is three bits.
In asynchronous mode the RxCL clock is turned off.
Integrating Capacitor
Diagnostic/Operational Modes
The ACS101A requires the use of an integrating ceramic capacitor
of value 10nF - 33nF between pins CNT and GND for a crystal
oscillator frequency range from 18MHz to 5MHz respectively.
The diagnostic/operational modes input pins DM1-DM3 may be
changed asynchronously within a window of (crystal clock period )
* 1536. The diagnostic mode signals are sampled 1536 * (crystal
PORB
clock period) after a change is detected on any of the DM inputs.
The sampled value is taken as the valid diagnostic mode.
The PORB pin is a single-pin alternative to the reset combination
DM3 = 0, DM2 = 0, and DM1 = 1. If left unconnected the input Diagnostic Mode
Lock
DM3 DM2 DM1
pulls High to the operational state. Selecting reset using DM1-
DM3 or holding PORB Low turns off the LED and most of the
digital logic. The device has been designed to power-up correctly
and operate without the aid of PORB.
Full-duplex
Reset
Remote loopback
Full-duplex
drift
active
random
0
0
0
0
0
1
0
1
0
0
1
1
Transmission Clock TxCL
Local loopback
drift
1
0
0
The ACS101A gives a choice between internally and externally
Full-duplex slave
Full-duplex master
active
drift
1
0
1
1
1
0
2
generated transmission clocks (see Figure 3. Timing diagrams for Full-duplex
active
1
1
1
set-up and hold specifications).
Full-Duplex
When the CKC pin is held Low, TxCL is configured as an output
producing a clock at the frequency defined by DR1-DR4. Data is In full-duplex configuration the RxCL clock of both devices tracks
clocked into the device on the rising edge of the internally supplied the average frequency of the TxCL clock of the opposing end of
clock.
the link. The receiving Digital Phase-Lock Loop (DPLL) system
When the CKC pin is held High, TxCL is configured as an input,
and will accept an externally produced transmission clock with a
tolerance of up to 500ppm with respect to the transmission rate
determined by DR1-DR4.
makes periodic adjustments to the RxCL clock to ensure that the
average frequency is exactly the same as the far-end TxCL clock.
In this mode each TxCL is an independent master clock and each
RxCL a slave clock.
The ACS101A performance is at its best when external changes
on input pins are synchronised with internal clocks. Therefore,
superior performance is likely when using the internally generated
data transmission clock. If however, the externally generated
transmission clock is used, then TxCL and TxD are generally
asynchronous to the ACS101A internal clocks, performance in this
case will be enhanced by limiting the edge speed of the TxCL and
TxD signals so that they are greater than 150 ns. The modem has
been designed to cope with very slow edges on inputs, without
fear of metastability problems.
Receive Clock RxCL
In synchronous mode data is valid on the rising edge of RxCL
clock (see Figure 3. Timing diagrams). To ensure that the
average receive frequency is the same as the transmitted
frequency RxCL is generated from a Digital Phase-Lock Loop
(DPLL) system. The DPLL makes periodic corrections to the
output RxCL clock to compensate for differences in the crystal
values, and in the case of an externally supplied transmission
clock, TxCL, compensation is also made for differences in
frequency between this supplied data clock and the selected clock
rate (DR1-DR4). The DPLL is adaptive and will minimise the
frequency of correction and jitter when the crystal values and
transmission clocks are tightly toleranced.
If the ACS101A receive FIFO empties (e.g. transmissions at far-
end are halted) the RxCL clock stops, therefore rising edges of the
RxCL clock always correspond to valid received data bits. This
Full-Duplex Slave
In slave mode the TxCL and the RxCL clock is derived from the
TxCL clock of the opposing side of the link, such that the average
frequency is exactly the same. It is therefore essential that only
one modem is configured in slave mode at a time. The CKC pin is
overridden such that TxCL is always configured as an output.
Full-Duplex Master
In master mode, the local RxCL clock is internally generated from
the local TxCL clock. The local TxCL clock may be internally or
externally generated. Master mode is only valid if the far-end
device is configured in slave mode or if the far-end TxCL clock is
derived from the far-end RxCL clock. Only one modem within a
communicating pair may be configured as a master.
Local Loopback
In local loopback mode data is looped back inside the near-end
modem and is output at its own RxD output. The data is also sent
to the far-end modem; synchronisation between the modems is
maintained. In local loopback mode data received from the far-
end device is ignored, except to maintain lock. When local
loopback is activated the DCDB signal assumes the logic High
state. If concurrent requests occur for local and remote loopback,
local loopback is selected.
When RSS = 0, RTS and DTR are looped back to CTS and DSR
respectively.
3
ACS101A Issue 1.2 October 1999.
Share Link: 