82559ER データシートの表示（PDF） - Intel

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82559ER

Fast Ethernet PCI Controller

Intel 

10.4.2.4 EEPROM Interface Timings

Networking Silicon — GD82559ER

FLADDR

FLCS#

FLOE#

FLDATA-R

Address Stable

T35

T37

T38

T36

T39

Data In

Figure 29. Flash Timings for a Read Cycle

The 82559ER is designed to support a standard 64x16, or 256x16 serial EEPROM. Table 27

provides the timing parameters for the EEPROM interface signals. The timing parameters are

illustrated in Figure 30.

Table 27. EEPROM Timing Parameters

Symbol

Parameter

T50 tEFSK

Serial Clock Frequency

T51 tECSS

Delay from EECS High to EESK High

T52 tECSH

Delay from EESK Low to EECS Low

T53 tEDIS

Setup Time of EEDI to EESK

T54 tEDIH

Hold Time of EEDI after EESK

T55 tECS

EECS Low Time

Min Max Units

Notes

1

Mhz

EEPROM fsk =

1 MHz

300

ns

EEPROM tcss

= 50 ns

30

ns

EEPROM tcsh

= 0 ns

300

ns

EEPROM tdis

= 150 ns

300

ns

EEPROM tdih

= 150 ms

750

ns

EEPROM tcs =

250 ns

Datasheet

81

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