82559ER データシートの表示（PDF） - Intel
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82559ER Datasheet PDF : 94 Pages
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Networking Silicon — GD82559ER
10.4.2.2
10.4.2.3
Table 24. Measure and Test Condition Parameters
Vstep (rising edge)
0.285VCC
Vstep (falling edge)
Vmax
Input Signal Edge
Rate
0.615VCC
0.4VCC
1
0.325VCC
0.475VCC
0.475VCC
0.325VCC
0.4VCC
1
V Min Delay
V Max Delay
V Min Delay
V Max Delay
V
V/ns
NOTE: Input test is done with 0.1VCC overdrive. Vmax specifies the maximum peak-to-peak waveform allowed
for testing input timing.
PCI Timings
Table 25. PCI Timing Parameters
Symbol
Parameter
Min
T14 tval
T15 tval(ptp)
T16 ton
T17 toff
T18 tsu
T19 tsu(ptp)
T20 th
T21 trst
T22 Trst-clk
T23 Trst-off
PCI CLK to Signal Valid Delay
2
PCI CLK to Signal Valid Delay (point-
to-point)
2
Float to Active Delay
2
Active to Float Delay
Input Setup Time to CLK
7
PCI Input Setup Time to CLK (point-to-
point)
10
Input Hold Time from CLK
0
Reset Active Time After Power Stable
1
PCI Reset Active Time After CLK
Stable
100
Reset Active to Output Float Delay
Max Units
11
ns
12
ns
ns
28
ns
ns
ns
ns
ms
µs
40
ns
Notes
1, 2, 4
1, 2, 4
1
1
4, 5
4, 5
6
6
6
6, 7
NOTES:
1. Timing measurement conditions are illustrated in Figure 27.
2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section
4.2.3.2.
3. n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times
and input setup times than bussed signals. All other signals are bussed.
4. Timing measurement conditions are illustrated in Figure 28.
5. RST# is asserted and de-asserted asynchronously with respect to the CLK signal.
6. All PCI interface output drivers are floated when RST# is active.
Flash Interface Timings
The 82559ER is designed to support up to 150 nanoseconds of Flash access time. The VPP signal in
the Flash implementation should be connected permanently to 12 V. Thus, writing to the Flash is
controlled only by the FLWE# pin.
Table 26 provides the timing parameters for the Flash interface signals. The timing parameters are
illustrated in Figure 29.
Datasheet
79
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