82559ER データシートの表示（PDF） - Intel

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82559ER

Fast Ethernet PCI Controller

Intel 

9.

9.1

9.1.1

Networking Silicon — GD82559ER

PHY Unit Registers

The 82559ER provides status and accepts management information via the Management Data

Interface (MDI) within the CSR space.

Acronyms mentioned in the registers are defined as follows:

SC -

self cleared

RO - read only

E-

EEPROM setting affects content

LL -

latch low

LH - latch high

MDI Registers 0 - 7

Register 0: Control Register Bit Definitions

Bit(s)

15

Name

Reset

14

Loopback

13

Speed Selection

12

Auto-Negotiation

Enable

11

Power-Down

10

Reserved

Description

Default R/W

This bit sets the status and control register of the PHY to

their default states and is self-clearing. The PHY returns

a value of one until the reset process has completed and

accepts a read or write transaction.

1 = PHY Reset

0

RW

SC

This bit enables loopback of transmit data nibbles from

the TXD[3:0] signals to the receive data path. The PHY

unit’s receive circuitry is isolated from the network.

Note that this may cause the descrambler to lose

synchronization and produce 560 nanoseconds of “dead

time.”

Note also that the loopback configuration bit takes priority

over the Loopback MDI bit.

1 = Loopback enabled

0 = Loopback disabled (Normal operation)

This bit controls speed when Auto-Negotiation is disabled

and is valid on read when Auto-Negotiation is disabled.

1 = 100 Mbps

0 = 10 Mbps

0

RW

1

RW

This bit enables Auto-Negotiation. Bits 13 and 8, Speed

Selection and Duplex Mode, respectively, are ignored

when Auto-Negotiation is enabled.

1 = Auto-Negotiation enabled

0 = Auto-Negotiation disabled

1

RW

This bit sets the PHY unit into a low power mode. In low

power mode, the PHY unit consumes no more than 30

mA.

1 = Power-Down enabled

0 = Power-Down disabled (Normal operation)

0

RW

This bit is reserved and should be set to 0b.

0

RW

Datasheet

65

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