82559ER データシートの表示（PDF） - Intel

部品番号

コンポーネント説明

メーカー

82559ER

Fast Ethernet PCI Controller

Intel 

4.5.1

4.5.2

4.5.3

4.5.4

Networking Silicon — GD82559ER

Full Duplex

When operating in full duplex mode the 82559ER can transmit and receive frames simultaneously.

Transmission starts regardless of the state of the internal receive path. Reception starts when the

internal PHY detects a valid frame on the receive differential pair of the PHY.

The 82559ER operates in either half duplex mode or full duplex mode. For proper operation, both

the 82559ER CSMA/CD module and the PHY unit must be set to the same duplex mode. The

CSMA duplex mode is set by the 82559ER Configure command or forced by automatically

tracking the mode in the PHY unit.

The PHY duplex mode is set either by Auto-Negotiation or, if Auto-Negotiation is disabled, by

setting the full duplex bit in the Management Data Interface (MDI) Register 0, bit 8. By default, the

internal PHY unit advertises full duplex ability in the Auto-Negotiation process regardless of the

duplex setting of the CSMA unit. The CSMA configuration should match the result of the Auto-

Negotiation.

The selection of duplex operation (full or half) and flow control is done in two levels: MAC and

PHY. The MAC duplex selection is done only through CSMA configuration mechanism (in other

words, the Configure command from software).

Flow Control

The 82559ER supports IEEE 802.3x frame based flow control frames only in both full duplex and

half duplex switched environments. The 82559ER flow control feature is not intended to be used in

shared media environments.

Flow control is optional in full duplex mode and can be selected through software configuration.

There are three modes of flow control that can be selected: frame based transmit flow control,

frame based receive flow control, and none.

The PHY unit’s duplex and flow control enable can be selected using NWay* Auto-Negotiation

algorithm or through the Management Data Interface.

Address Filtering Modifications

The 82559ER can be configured to ignore one bit when checking for its Individual Address (IA) on

incoming receive frames. The address bit, known as the Upper/Lower (U/L) bit, is the second least

significant bit of the first byte of the IA. This bit may be used, in some cases, as a priority

indication bit. When configured to do so, the 82559ER passes any frame that matches all other 47

address bits of its IA, regardless of the U/L bit value.

This configuration only affects the 82559ER specific IA and not multicast, multi-IA or broadcast

address filtering. The 82559ER does not attribute any priority to frames with this bit set, it simply

passes them to memory regardless of this bit.

Long Frame Reception

The 82559ER supports the reception of long frames, specifically frames longer than 1518 bytes,

including the CRC, if software sets the Long Receive OK bit in the Configuration command

(described in the Software Developer’s Manual). Otherwise, “long” frames are discarded.

Datasheet

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