SSD1801Z データシートの表示（PDF） - Solomon Systech

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SSD1801Z

LCD Segment / Common Driver with Controller for Character Display System

Solomon Systech  

VF

This pin is the input of the built-in voltage regulator. When external resistor network is selected to generate the

LCD driving level, VL6, two external resistors, R1 and R2, are connected between AVSS and VF, and VF and VL6,

respectively (see application circuit)

VOUT

Regulated DC/DC voltage converter output. External capacitor is connected to AVDD for internal regulated DC-

DC converter and divider mode only.

VEXT

This is an input pin to provide an external voltage reference for the internal voltage regulator. It is selected by REF

signal pin. Leave this pin open (NC) if internal voltage regulator is used.

REF

This pin is to select the input voltage of internal voltage regulator. When this pin is pulled low, the internal voltage

reference VREF is used. When this pin is pulled high, external voltage reference (VEXT) is selected.

DIRS

This pin controls the direction of Segment.

When DIRS = Low

SEG0 -> SEG2 -> ..... -> SEG78 -> SEG79

When DIRS = High

SEG79 -> SEG78 -> ..... -> SEG1 -> SEG0

CLK

External clock input. It must be fixed to high or low when the internal oscillation circuit is used. In case of the

external clock mode, CLK is used as the clock and OSC bit should be OFF.

P/ S

This pin is serial/ parallel interface selection input. When this pin is pulled high, parallel mode is selected. When it

is pulled low, serial interface will be selected. Read back operation is only available in parallel mode.

DL

This pin is to select the data length for parallel data input.

When P/ S = Low

DL = Low or High: serial interface mode

When P/ S = High

DL = Low: 4-bit bus mode

DL = High: 8-bit bus mode

This pin must be fixed to high or low in serial mode.

C68/ 80

This pin is microprocessor interface selection input. When the pin is pulled high, 6800 series interface is selected

and when the pin is pulled low, 8080 series MCU interface is selected. This pin must be fixed to high or low in serial

mode.

RES

This pin is reset signal input. Initialization of the chip is started once this pin is pulled low. Minimum pulse width for

completing the reset is 10ms.

TEST

Test pin. This pin is not used for normal operation. Leave this pin open (NC).

C1P, C1N, C2P and C2N

When internal DC-DC voltage converter is used, external capacitors are connected between these pins. Different

connection will result in different DC-DC converter multiple factor, 2x/3x. Details connections please refer to Figure

12.

SOLOMON

Rev 1.1

01/2003

10

SSD1801 Series

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