FDC37C93X データシートの表示（PDF） - SMSC -> Microchip

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FDC37C93X

Plug and Play Compatible Ultra I/O™ Controller

SMSC -> Microchip 

TAPE DRIVE REGISTER (TDR)

Address 3F3 READ/WRITE

This register is included for 82077 software

compatability. The robust digital data separator

used in the FDC does not require its

characteristics modified for tape support. The

contents of this register are not used internal to

the device. The TDR is unaffected by a

software reset. Bits 2-7 are tri-stated when

read in this mode.

Table 4- Tape Select Bits

TAPE SEL1

0

0

1

1

TAPE SEL2

0

1

0

1

DRIVE

SELECTED

None

1

2

3

Table 5 - Internal 2 Drive Decode - Normal

DIGITAL OUTPUT REGISTER

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0

nDS1

nDS0

nMTR1

nMTR0

X

X

X

1

0

0

1

0

nBIT 5

nBIT 4

X

X

1

X

0

1

0

1

nBIT 5

nBIT 4

X

1

X

X

1

0

1

1

nBIT 5

nBIT 4

1

X

X

X

1

1

1

1

nBIT 5

nBIT 4

0

0

0

0

X

X

1

1

nBIT 5

nBIT 4

Table 6 - Internal 2 Drive Decode - Drives 0 and 1 Swapped

DIGITAL OUTPUT REGISTER

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0

nDS1

nDS0

nMTR1

nMTR0

X

X

X

1

0

0

0

1

nBIT 4

nBIT 5

X

X

1

X

0

1

1

0

nBIT 4

nBIT 5

X

1

X

X

1

0

1

1

nBIT 4

nBIT 5

1

X

X

X

1

1

1

1

nBIT 4

nBIT 5

0

0

0

0

X

X

1

1

nBIT 4

nBIT 5

18

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