LPC61W492 データシートの表示（PDF） - SMSC -> Microchip

部品番号

コンポーネント説明

一致するリスト

LPC61W492

Integrated Super I/O Controller for LPC Bus with Game and MIDI Ports/Plus Hardware Monitoring Functions

SMSC -> Microchip 

LPC (LOW PIN COUNT) INTERFACE

LPC interface is to replace ISA interface serving as a bus interface between host (chip-set) and

peripheral (SMSC I/O). Data transfer on the LPC bus are serialized over a 4 bit bus. The general

characteristics of the interface implemented in SMSC LPC I/O are:

%# One control line, namely nLFRAME, which is used by the host to start or stop transfers. No

peripherals drive this signal.

%# The LAD[3:0] bus, which communicates information serially. The information conveyed are

cycle type, cycle direction, chip selection, address, data, and wait states.

%# MR (master reset) of SMSC ISA I/O is replaced with an active low reset signal, namely

nLRESET, in SMSC LPC I/O.

%# An additional 33 MHz PCI clock is needed in SMSC LPC I/O for synchronization.

%# DMA requests are issued through nLDRQ.

%# Interrupt requests are issued through SERIRQ.

%# Power management events are issued through nPME.

Comparing to its ISA counterpart, LPC implementation saves up to 40 pins (see table below) which are

free for integrating more devices on a single chip.

SMSC I/O

INTERFACE PINS

COUNT

FDC37M72x D[7:0], SA[15:0], DRQ[3:0], DnACK[3:0], TC, nIOR, nIOW,

49

IOCHRDY, IRQs

LPC61W492 LAD[3:0], nLFRAME, PCICLK, nLDRQ, SERIRQ, nPME

9

save

40

The transition from ISA to LPC is transparent in terms of software which means no BIOS or device

driver update is needed except chip-specific configuration.

21

Share Link: