GM2121 データシートの表示（PDF） - Genesis Microchip
部品番号
コンポーネント説明
一致するリスト
GM2121
Genesis Microchip
GM2121 Datasheet PDF : 51 Pages
| |||
gm2121 Preliminary Data Sheet
3 GM2121Pin List
I/O Legend: A = Analog, I = Input, O = Output, P = Power, G= Ground
Pin Name
AVDD_RED_3.3
RED+
RED-
AGND_RED
AVDD_GREEN_3.3
GREEN+
GREEN-
AGND_GREEN
AVDD_BLUE_3.3
BLUE+
BLUE-
AGND_BLUE
AVDD_ADC_3.3
ADC_TEST
AGND_ADC
SGND_ADC
GND1_ADC
VDD1_ADC_2.5
GND2_ADC
VDD2_ADC_2.5
HSYNC
VSYNC
No.
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
101
100
I/O
AP
AI
AI
AG
AP
AI
AI
AG
AP
AI
AI
AG
AP
AO
AG
AG
G
P
G
P
I
I
Table 1. Analog Input Port
Description
Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor to
AGND_RED pin on system board (as close as possible to the pin).
Positive analog input for Red channel.
Negative analog input for Red channel.
Analog ground for the red channel.
Must be directly connected to the system ground plane.
Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor to
AGND_GREEN pin on system board (as close as possible to the pin).
Positive analog input for Green channel.
Negative analog input for Green channel.
Analog ground for the green channel.
Must be directly connected to the system ground plane.
Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor to
AGND_BLUE pin on system board (as close as possible to the pin).
Positive analog input for Blue channel.
Negative analog input for Blue channel.
Analog ground for the blue channel.
Must be directly connected to the system ground plane.
Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes
band gap reference, master biasing and full-scale adjust. Must be bypassed with
decoupling capacitor to AGND_ADC pin on system board (as close as possible to the pin).
Analog test output for ADC Do not connect.
Analog ground for ADC analog blocks that are shared by all three channels. Includes band
gap reference, master biasing and full-scale adjust.
Must be directly connected to system ground plane.
Dedicated pad for substrate guard ring that protects the ADC reference system.
Must be directly connected to the system ground plane.
Digital GND for ADC clocking circuit.
Must be directly connected to the system ground plane
Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to
GND1_ADC pin on system board (as close as possible to the pin).
Digital GND for ADC clocking circuit.
Must be directly connected to the system ground plane.
Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to
GND2_ADC pin on system board (as close as possible to the pin).
ADC input horizontal sync input.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
ADC input vertical sync input.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
Pin Name
AVDD_RPLL_3.3
AVSS_RPLL
TCLK
XTAL
VDD_DPLL_3.3
VSS_DPLL
Table 2. RCLK PLL Pins
No I/O Description
104 AP
105 AG
102 AI
103 AO
106 P
107 G
Analog power for the Reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a
0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible).
Analog ground for the Reference DDS PLL.
Must be directly connected to the system ground plane.
Reference clock (TCLK) from the 20.0MHz crystal oscillator (see Figure 4), or from single-
ended CMOS/TTL clock oscillator (see Figure 7). This is a 5V-tolerant input. See Table 12.
Crystal oscillator output.
Digital power for FCLK and RCLK PLLs. Connect to 3.3V supply.
Digital ground for FCLK and RCLK PLLs.
C2121-DAT-01F
11
http://www.genesis-microchip.com
December 2002
Share Link: