FS6209 データシートの表示（PDF） - AMI Semiconductor
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FS6209 Datasheet PDF : 6 Pages
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February 1999
Table 5: DC Electrical Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP. MAX. UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
Voltage Controlled Crystal Oscillator
Crystal Resonator Frequency
Crystal Loading Capacitance
Crystal Resonator Motional Capacitance
VCXO Tuning Range
VCXO Tuning Characteristic
Crystal Drive Level
Clock Outputs (CLKA, CLKB, CLKC)
High-Level Output Source Current *
Low-Level Output Sink Current *
Output Impedance *
Short Circuit Source Current *
Short Circuit Sink Current *
IDD
fXTAL = 13.5MHz; CL = 10pF
fXTAL
Fundamental Mode
5.
CL(xtal)
As seen by a crystal connected to XIN and
XOUT (@ VXTUNE = 1.65V)
C1(xtal)
AT cut
fXTAL = 13.5MHz; CL = 20pF; CMOT = 25fF
Note: positive -F for positive -V
RXTAL=20 ohm; CL = 20pF
IOH
VO = 2.0V
IOL
VO = 0.4V
zOH
VO = 0.1VDD; output driving high
zOL
VO = 0.1VDD; output driving low
IOSH
VO = 0V; shorted for 30s, max.
IOSL
VO = 3.3V; shorted for 30s, max.
20
13.5
20
25
300
100
200
40
17
25
25
55
55
mA
18
MHz
pF
fF
ppm
ppm/V
uW
mA
mA
Ω
mA
mA
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX. UNITS
Clock Outputs (CLKx)
Duty Cycle *
Jitter, Absolute Period (pk-pk) *
Jitter, RMS Long Term (σy(τ)) *
Rise Time *
Fall Time *
Output Frequency Synthesis Error
VCXO Stabilization Time *
PLL Stabilization Time *
tj(∆P)
tj(LT)
tr
tf
tVCXOSTB
tPLLSTB
thi / tclk; Measured at VDD/2
From rising edge to next rising edge at
VDD/2, CL = 10pF
From 0-500µs at VDD/2, CL = 10pF
compared to ideal clock source
VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF
VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF
(unless otherwise noted in Frequency Table)
From power valid
From VCXO stable
43
57
%
300
ps
150
ps
1
ns
1
ns
0
ppm
10
ms
500
us
4
,62
2.4.99
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