ADIS16209(Rev0) データシートの表示（PDF） - Analog Devices

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ADIS16209
(Rev.:Rev0)

High-Accuracy, Dual-Axis Digital Inclinometer and Accelerometer

Analog Devices 

ADIS16209

TIMING SPECIFICATIONS

TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.

Table 2.

Parameter

fSCLK

tDATARATE

tCS

tDAV

tDSU

tDHD

tDF

tDR

tSFS

Description

Fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 546 Hz)2

Normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 482 Hz)2

Chip select period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 546 Hz)2

Chip select period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 482 Hz)2

Chip select to clock edge

Data output valid after SCLK edge

Data input setup time before SCLK rising edge

Data input hold time after SCLK rising edge

Data output fall time

Data output rise time

CS high after SCLK edge

1 Guaranteed by design, not tested.

2 Note that fS means internal sample rate.

TIMING DIAGRAMS

CS

tDATARATE

tSTALL

SCLK

tSTALL = tDATARATE – 16/fSCLK

Figure 2. SPI Chip Select Timing

Min1

0.01

0.01

40

100

48.8

24.4

48.8

5

Typ

Max

Unit

2.5

MHz

1.0

MHz

μs

μs

ns

100

ns

ns

ns

5

12.5

ns

5

12.5

ns

ns

CS

SCLK

DOUT

DIN

tCS

1

MSB

W/R

2

3

4

5

6

tDAV

DB14

tDSU

DB13

DB12

tDHD

DB11

DB10

A5

A4

A3

A2

15

16

tSFS

DB2

DB1

LSB

D2

D1

LSB

Figure 3. SPI Timing

(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)

CS

SCLK

DIN

W/R

DATA FRAME

A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

WRITE = 1

READ = 0

REGISTER ADDRESS

DATA FOR WRITE COMMANDS

DON’T CARE FOR READ COMMANDS

Figure 4. DIN Bit Sequence

Rev. 0 | Page 5 of 16

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