NQ6311 データシートの表示（PDF） - Unspecified

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NQ6311

Intel® 631xESB/632xESB I/O Controller Hub

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5.21

5.22

5.23

5.24

5.20.3 Data Encoding and Bit Stuffing ............................................................ 239

5.20.4 Bus Protocol ...................................................................................... 239

5.20.5 Packet Formats.................................................................................. 240

5.20.6 USB Interrupts .................................................................................. 240

5.20.7 USB Power Management ..................................................................... 242

5.20.8 USB Legacy Keyboard Operation .......................................................... 243

USB EHCI Host Controller (D29:F7).................................................................... 246

5.21.1 EHC Initialization ............................................................................... 246

5.21.2 Data Structures in Main Memory .......................................................... 247

5.21.3 USB 2.0 Enhanced Host Controller DMA ................................................ 247

5.21.4 Data Encoding and Bit Stuffing ............................................................ 247

5.21.5 Packet Formats.................................................................................. 247

5.21.6 USB 2.0 Interrupts and Error Conditions ............................................... 247

5.21.7 USB 2.0 Power Management................................................................ 248

5.21.8 Interaction with UHCI Host Controllers .................................................. 250

5.21.9 USB 2.0 Legacy Keyboard Operation..................................................... 252

5.21.10 USB 2.0 Based Debug Port .................................................................. 252

SMBus............................................................................................................ 257

5.22.1 SMBus Controller (D31:F3).................................................................. 257

5.22.2 SMBus Slave Interface in PCI Express to PCI-X Bridge............................. 269

AC’97 Controller (Audio D31:F5, Modem D31:F6)................................................. 276

5.23.1 PCI Power Management ...................................................................... 278

5.23.2 AC-Link Overview .............................................................................. 279

5.23.3 AC-Link Low Power Mode .................................................................... 282

5.23.4 AC’97 Cold Reset ............................................................................... 283

5.23.5 AC’97 Warm Reset ............................................................................. 283

5.23.6 Hardware Assist to Determine ACZ_SDIN Used Per Codec ....................... 284

Intel® High Definition Audio Controller Overview ................................................. 284

6 Electrical Characteristics........................................................................................ 287

7 Component Ballout................................................................................................. 303

7.1 Intel® 631xESB/632xESB I/O Controller Hub Ballout ............................................ 303

8 Signal Lists ............................................................................................................ 307

8.1 Intel® 631xESB/632xESB I/O Controller Hub Signal List (Sorted by Signal Name) .... 307

8.2 Intel® 631xESB/632xESB I/O Controller Hub Signal List (Sorted by Ball Number)..... 323

9 Mechanical Specifications ...................................................................................... 339

10 Testability.............................................................................................................. 343

10.1 JTAG Test Mode Description .............................................................................. 343

10.2 XOR Chain Test Mode Description ...................................................................... 344

10.2.1 XOR Chain Testability Algorithm Example .............................................. 345

10.3 XOR Chain Tables ............................................................................................ 345

11 Register and Memory Mapping ............................................................................... 351

11.1 Register Nomenclature and Access Attributes ...................................................... 351

11.2 PCI Devices and Functions ................................................................................ 352

11.3 PCI Configuration Map ...................................................................................... 353

11.4 I/O Map.......................................................................................................... 353

11.4.1 Fixed I/O Address Ranges ................................................................... 353

11.4.2 Variable I/O Decode Ranges ................................................................ 355

11.5 Memory Map ................................................................................................... 356

12 Chipset Configuration Registers ............................................................................. 359

12.1 Chipset Configuration Registers (Memory Space) ................................................. 359

12.1.1 VCH – Virtual Channel Capability Header Register................................... 361

12.1.2 VCAP1 – Virtual Channel Capability #1 Register ..................................... 361

12.1.3 VCAP2 – Virtual Channel Capability #2 Register ..................................... 361

8

Intel® 631xESB/632xESB I/O Controller Hub Datasheet

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