82801HB データシートの表示（PDF） - Unspecified

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82801HB

Intel® I/O Controller Hub 8 (ICH8) Family

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8.1.17 INTR—Interrupt Information Register (Gigabit LAN—D25:F0)...................... 316

8.1.18 MLMG—Maximum Latency/Minimum Grant Register

(Gigabit LAN—D25:F0) .......................................................................... 316

8.1.19 CLIST 1—Capabilities List Register 1 (Gigabit LAN—D25:F0) ....................... 317

8.1.20 PMC—PCI Power Management Capabilities Register

(Gigabit LAN—D25:F0) .......................................................................... 317

8.1.21 PMCS—PCI Power Management Control and Status

Register (Gigabit LAN—D25:F0) .............................................................. 318

8.1.22 DR—Data Register (Gigabit LAN—D25:F0)................................................ 318

8.1.23 CLIST 2—Capabilities List Register 2 (Gigabit LAN—D25:F0) ....................... 319

8.1.24 MCTL—Message Control Register (Gigabit LAN—D25:F0) ............................ 319

8.1.25 MADDL—Message Address Low Register (Gigabit LAN—D25:F0) .................. 319

8.1.26 MADDH—Message Address High Register (Gigabit LAN—D25:F0)................. 320

8.1.27 MDAT—Message Data Register(Gigabit LAN—D25:F0) ................................ 320

8.2 GBAR0—Gigabit LAN Base Address Register 0 Registers ........................................ 321

8.2.1 LDCR1—LAN Device Control Register 1

(Gigabit LAN Memory Mapped Base Address Register) ............................... 321

8.2.2 LDCR2—LAN Device Control Register 2

(Gigabit LAN Memory Mapped Base Address Register) ............................... 321

8.2.3 LDR1—LAN Device Initialization Register 1

(Gigabit LAN Memory Mapped Base Address Register) ............................... 321

8.2.4 EXTCNF_CTRL—Extended Configuration Control Register

(Gigabit LAN Memory Mapped Base Address Register) ............................... 322

8.2.5 LDR2—LAN Device Initialization Register 2

(Gigabit LAN Memory Mapped Base Address Register) ............................... 322

9 LPC Interface Bridge Registers (D31:F0) ............................................................... 323

9.1 PCI Configuration Registers (LPC I/F—D31:F0) .................................................... 323

9.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) .............................. 324

9.1.2 DID—Device Identification Register (LPC I/F—D31:F0)............................... 324

9.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)................................. 325

9.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)........................................ 325

9.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ............................ 326

9.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) ............................. 326

9.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) ..................................... 327

9.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0) .................................... 327

9.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) ............................ 327

9.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0) .................................. 327

9.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0) ............................. 328

9.1.12 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) ........................... 328

9.1.13 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0) ............................. 329

9.1.14 GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0) ..................... 329

9.1.15 GC—GPIO Control Register (LPC I/F — D31:F0) ........................................ 330

9.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0) ................................................................................ 330

9.1.17 SIRQ_CNTL—Serial IRQ Control Register (LPC I/F—D31:F0) ....................... 331

9.1.18 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0) ................................................................................ 332

9.1.19 LPC_I/O_DEC—I/O Decode Ranges Register (LPC I/F—D31:F0)................... 333

9.1.20 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) ................................ 334

9.1.21 GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0) ................................................................................ 335

9.1.22 GEN2_DEC—LPC I/F Generic Decode Range 2Register

(LPC I/F—D31:F0) ................................................................................ 335

9.1.23 GEN3_DEC—LPC I/F Generic Decode Range 3Register

(LPC I/F—D31:F0) ................................................................................ 336

12

Intel® ICH8 Family Datasheet

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