FAN5355 データシートの表示（PDF） - Fairchild Semiconductor

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FAN5355

1A / 0.8A, 3MHz Digitally Programmable TinyBuck™ Regulator

Fairchild Semiconductor 

Output Voltage Transitions

The IC regulates VOUT to one of two setpoint voltages, as

determined by the VSEL pin and the HW_nSW bit.

VSEL Pin HW_nSW Bit VOUT Setpoint(14) PFM

0

1

VSEL0

Allowed

1

1

VSEL1

Per MODE1

x

0

VSEL1

Per MODE1

Table 8. VOUT Setpoint and Mode Control MODE_CTRL,

CONTROL1[3:2] = 00

Note:

14. Option 07 uses VSELx[6:0] to set VOUT, while all other

options use VSELx[5:0].

If HW_nSW =0, VOUT transitions are initiated through the

following sequence:

1. Write the new setpoint in VSEL1.

2. Write desired transition rate in DEFSLEW,

CONTROL2[2:0], and set the GO bit in CONTROL2[7].

If HW_nSW =1, VOUT transitions are initiated either by

changing the state of the VSEL pin or by writing to the VSEL

register selected by the VSEL pin.

Positive Transitions

When transitioning to a higher VOUT, the regulator can

perform the transition using multi-step or single-step mode.

Multi-step Mode:

The internal DAC is stepped at a rate defined by

DEFSLEW, CONTROL2[2:0], ranging from 000 to 110. This

mode minimizes the current required to charge COUT and

thereby minimizes the current drain from the battery when

transitioning. The PWROK bit, CONTROL2[5], remains

LOW until about 1.5μs after the DAC completes its ramp.

VHIGH

VOUT

VLOW

VSEL

PWROK

tPOK(L-H)

Figure 36. Multi-step VOUT Transition

Single-step Mode:

Used if DEFSLEW, CONTROL2[2:0] = 111. The internal

DAC is immediately set to the higher voltage and the

regulator performs the transition as quickly as its current

limit circuit allows, while avoiding excessive overshoot.

Figure 37 shows single-step transition timing. tV(L-H) is the

time it takes the regulator to settle to within 2% of the new

setpoint and is typically 7μs for a full-range transition (from

00000 to 11111 for 6-bit DAC options). The PWROK bit,

CONTROL2[5], goes LOW until the transition is complete

and VOUT settled. This typically occurs ~2μs after tV(L-H).

It is good practice to reduce the load current before making

positive VSEL transitions. This reduces the time required to

make positive load transitions and avoids current–limit-

induced overshoot.

VHIGH

tV(L-H)

98% VHIGH

VOUT

VSEL

PWROK

VLOW

tPOK(L-H)

Figure 37. Single-Step VOUT Transition

All positive VOUT transitions inhibit PFM until the transition is

complete, which occurs at the end of tPOK(L-H).

Negative Transitions

When moving from VSEL=1 to VSEL=0, the regulator

enters PFM mode, regardless of the condition of the SYNC

pin or MODE bits, and remains in PFM until the transition is

completed. Reverse current through the inductor is blocked,

and the PFM minimum frequency control inhibited, until the

new setpoint is reached, at which time the regulator

resumes control using the mode established by

MODE_CTRL. The transition time from VHIGH to VLOW is

controlled by the load current and output capacitance as:

t V(H−L)

=

COUT

•

VHIGH − VLOW

ILOAD

(4)

VHIGH

VOUT

VSEL

PWROK

VLOW

tV(L-H)

tPOK(L-H)

Figure 38. Negative VOUT Transition

© 2008 Fairchild Semiconductor Corporation

20

FAN5355 • Rev. 1.0.4

www.fairchildsemi.com

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