WJLXT972MLC.A4 データシートの表示（PDF） - Intel

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WJLXT972MLC.A4

Single-Port 10/100 Mbps PHY Transceiverv

Intel 

Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Contents

1.0

Introduction to This Document ......................................................................................... 10

1.1 Document Overview ............................................................................................10

1.2 Related Documents............................................................................................. 10

2.0

Block Diagram for Intel® LXT972M Transceiver............................................................... 11

3.0

Pin Assignments for Intel® LXT972M Transceiver ...........................................................12

4.0

Signal Descriptions for Intel® LXT972M Transceiver ....................................................... 15

5.0

Functional Description...................................................................................................... 21

5.1 Device Overview .................................................................................................22

5.1.1 Comprehensive Functionality ................................................................. 22

5.1.2 Optimal Signal Processing Architecture ................................................. 22

5.2 Network Media / Protocol Support.......................................................................23

5.2.1 10/100 Network Interface .......................................................................23

5.2.2 MII Data Interface ................................................................................... 25

5.2.3 Configuration Management Interface ..................................................... 25

5.3 Operating Requirements .....................................................................................28

5.3.1 Power Requirements ..............................................................................28

5.3.2 Clock Requirements ............................................................................... 28

5.4 Initialization.......................................................................................................... 29

5.4.1 MDIO Control Mode and Hardware Control Mode .................................31

5.4.2 Reduced-Power Modes .......................................................................... 31

5.4.3 Reset for Intel® LXT972M Transceiver................................................... 31

5.4.4 Hardware Configuration Settings ...........................................................33

5.5 Establishing Link .................................................................................................34

5.5.1 Auto-Negotiation.....................................................................................34

5.5.2 Parallel Detection ................................................................................... 35

5.6 MII Operation....................................................................................................... 36

5.6.1 MII Clocks............................................................................................... 37

5.6.2 Transmit Enable .....................................................................................38

5.6.3 Receive Data Valid ................................................................................. 38

5.6.4 Carrier Sense ......................................................................................... 39

5.6.5 Error Signals........................................................................................... 39

5.6.6 Collision .................................................................................................. 39

5.6.7 Loopback................................................................................................ 40

5.7 100 Mbps Operation ............................................................................................41

5.7.1 100BASE-X Network Operations ...........................................................41

5.7.2 Collision Indication ................................................................................. 44

5.7.3 100BASE-X Protocol Sublayer Operations ............................................ 45

5.8 10 Mbps Operation.............................................................................................. 50

5.8.1 10BASE-T Preamble Handling ............................................................... 50

5.8.2 10BASE-T Carrier Sense .......................................................................50

5.8.3 10BASE-T Dribble Bits ........................................................................... 50

5.8.4 10BASE-T Link Integrity Test ................................................................. 51

5.8.5 Link Failure ............................................................................................. 51

Datasheet

3

Document Number: 302875-005

Revision Date: 27-Oct-2005

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