TDA8755T データシートの表示（PDF） - Philips Electronics

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TDA8755T

YUV 8-bit video low-power analog-to-digital interface

Philips Electronics 

Philips Semiconductors

YUV 8-bit video low-power

analog-to-digital interface

Product specification

TDA8755

handbook, full pagewidth

sample N

sample N 4

CLK

1

2

3

4

5

HREF

output

data

t su

N4

N3

N2

N1

sample N

output data valid

N

th

MLA732 - 1

The output data is valid 4 clock periods after HREF goes HIGH.

Fig.6 Timing definition for set-up and hold times (HREF signal).

handbook, full pagewidthsample N

CLK

4 clock periods (Tclk )

HREF

output

data

N4

N3

N3

sample N 4 x T clk

sample N 4 (Tclk 1)

output data valid

MLA731 - 1

When the HREF period is a multiple of 4 clock periods, the output data is valid without any clock delay.

The internal circuit always gives an internal delay of 4 clock periods as illustrated in Fig.6.

Fig.7 Timing diagram (HREF signal).

1995 Mar 09

11

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