TDA8758G データシートの表示（PDF） - Philips Electronics

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TDA8758G

YC 8-bit low-power analog-to-digital video interface

Philips Electronics 

Philips Semiconductors

YC 8-bit low-power analog-to-digital video

interface

Product specification

TDA8758

FUNCTIONAL DESCRIPTION

The TDA8758 provides a simple interface between CVBS

or Y/C analog signals and a digital colour decoder.

Video inputs selection

The input selector allows a choice from different video

sources, and has one of the following configurations:

A: Two Y/C and one CVBS signals

B: One Y/C and two CVBS signals

C: Three CVBS signals (only the Y channel is used).

The wiring of the five video inputs (pins 2, 4, 6, 9 and 11)

and the control of the two selection inputs (pins 5 and 12)

will depend on the available video sources.

• In configuration A, connect as follows:

– Y1 to pin 11

– C1 to pin 4

– Y2 to pin 9

– C2 to pin 2

– CVBS3 to pin 6.

Keep SEL2 (pin 5) LOW and select Y1/C1 or Y2/C2 by

switching SEL1 (pin 12).

CVBS3 is selected with SEL1 and SEL2 HIGH.

• In configuration B, replace Y1 (or Y2) by a CVBS input

(no more C1 or C2). The selection mode is the same.

• In configuration C, connect as follows:

– CVBS1 to pin 11

– CVBS2 to pin 9

– CVBS3 to pin 6.

Use both SEL1 and SEL2 to select inputs.

Remark: the video inputs selection is a static selection.

Synchronization pulses

GATE A and GATE B pulses are synchronization pulses

occurring during the sync period and rear porch

respectively. They should be distinct.

On the Y channel, the digital output of the ADC is

compared to internal digital reference levels. The resultant

outputs control the charge or discharge current of a

capacitor connected to the CAGC pin. The voltage across

this capacitor controls the gain of the video amplifier.

This is the control loop.

The sync level comparator is active during a positive-going

pulse at the GATE A input. This means that sync pulse of

the composite video signal is used as an amplitude

reference. The bottom of the sync pulse is adjusted to

obtain a digital output of logic 1 at the converter Y output.

As the black level is digital level 64, the sync pulse will

have a digital amplitude of 64 LSBs.

The Peak White control loop is active when the selection

pin PWE is LOW. Then, if the Y video signal exceeds the

digital code of 255, it will be limited to avoid any over-range

of the converter.

The clamp level control is accomplished by using the same

techniques as used for the gain control. On both Y and C

channels, the black level digital comparators are active

during a positive-going pulse at the GATE B input. On the

Y channel, the clamping capacitor connected to the CCLPY

pin will be charged or discharged to adjust the digital

output to code 64. On the C channel, the clamping

capacitor connected to the CCLPC pin will be charged or

discharged to adjust the digital output to code 128.

1996 Feb 01

6

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