CS22210 データシートの表示（PDF） - Cirrus Logic

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CS22210

Wireless PCI/USB Controller

Cirrus Logic 

nCBE[3:0]

IDSEL

nFRAME

NIRDY

nTRDY

nDEVSEL

nSTOP

nINTA

PCLK

nPERR

Bi-directional

Control/byte enable. This bus defines the bus command during the first

clock of a PCI transaction and the data byte enables during subsequent

clocks.

I/O OD

PCI initialization device select. Used as a chip select during configuration

read and write cycles.

Bi-directional

PCI cycle frame. This signal marks the beginning and duration of a

current bus cycle.

Bi-directional

PCI initiator ready. IRDY holds off the beginning of a write cycle and the

completion of a read cycle until sampled active.

Bi-directional

PCI target ready. This signal is driven active to indicate that write data

has been sampled or that read data has been delivered.

Bi-directional

PCI device select. As a medium speed device, this signal is driven active

two PCI clocks after NFRAME is sampled active, indicating a positive

decode. It remains active until the end of the transaction.

Bi-directional

PCI stop. This signal indicates a target initiated termination of the current

cycle.

Output/Open Drain

PCI interrupt request A. Generates an interrupt on the PCI bus.

I/O OD

PCI clock. Typically a 33 MHz. All CS22210 PCI activity is synchronous to

PCLK.

Bi-directional

PCI parity error. This signal is asserted two clocks after a data parity error

is detected on the PCI bus.

CS22210 PCI/USB Wireless Controller

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D556PP2 Rev. 3.0

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