MM1327XD データシートの表示（PDF） - Mitsumi

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MM1327XD

Wide Discriminator

Mitsumi 

MITSUMI

Wide Discriminator MM1327

Timing Chart 2

100IRE

Y input

50IRE

0IRE

I (Q) input

MAX output

tegrated output

S/H

GP

HD

ADCLX

DATA

PEAK 05

00

1. The largest of Y, I and Q video input signals is output on MAX output pin.

2. MAX output date is integrated during horizontal scanning.

3. Integration results are sampled and held at HD pulse timing.

4. Consecutive comparison ADC outputs data as serial data.

(Serial data is 1H delayed from video signal input.)

5. Output data configuration is as shown in the table below.

Data configuration

Y input

PEAK

Video

DATA

Peak of more than 50IRE

1

White scanning 00

No peak of more than 50IRE

0

Black scanning 3F

Timing Chart 3

10110

50IRE

+0.15V

-0.15

3FM

00M

YIN (22H)

NRZCLK

Integrated NRZCLK

(Internal circuit)

DELAY

NRZ discrimination timing

1. When YIN input signal matches "10110" at NRZ discrimination timing, it is identified as an EDTV2 signal.

EDTV2 pin is high for EDTV2 identification.

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