TEA6425
Figure 2. Block Diagram
1
PROG.
CLAMP
3
PROG.
CLAMP
5
PROG.
CLAMP
6
PROG.
CLAMP
8
PROG.
CLAMP
10
PROG.
CLAMP
6x8
MATRIX
SCL 4
SDA 2
SUB-ADDRESS 7
I2C
DECODER
VCC1 9
VCC2 20
TEA6425
0/6 0/6 0/6 0/6 0/6 0/6 0/6 0/6
dB dB dB dB dB dB dB dB
3 STATE OUTPUTS
11
12
13
14
15
16
17
18
19
GND
OUTPUTS
Figure 3. Cellular Matrix Connections
1st/4 addresses
CVBS
or C
I2 C
DECODER
PROG.
CLAMP
6X8
Full MATRIX
IC1
ADDER
0dB
6dB
3 STATE
OUT
2nd/4 addresses
I2 C
DECODER
6X8
Full
MATRIX
IC2
IC3
IC4
8 OUTPUTS LINES
2/10
1