UTR200 データシートの表示（PDF） - Aeroflex UTMC

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UTR200

UTR 0.8μ Gate Array Family

Aeroflex UTMC 

DEVICE PART NUMBERS1

UTR25

UTR35

UTR50

UTR75

UTR100

UTR150

UTR200

Table 1. Gate Densities

EQUIVALENT USABLE GATES2 SIGNAL I/O3

5,000 - 25,000

175

35,000

175

50,000

175

75,000

256

125,000

256

150,000

256

200,000

256

POWER & GROUND PADS4

40

40

40

80

80

80

80

Notes:

1. The "R" denotes radiation-hardened.

2. Based on NAND2 equivalents. Actual usable gate count is design-dependent. Estimates reflect a mix of functions including RAM.

3. Includes five pins that may or may not be reserved for JTAG boundary-scan, depending on user requirements.

4. Reserved for dedicated VDD/VSS and VDDQ/VSSQ.

Low-noise Device and Package Solutions

The UTR 0.8µ output drivers feature programmable slew rate

control for minimizing noise and switching transients. This fea-

ture allows the user to optimize edge characteristics to match

system requirements. Separate on-chip power and ground buses

are provided for internal cells and output drivers which further

isolate internal design circuitry from switching noise.

In addition, UTMC offers advanced low-noise package technol-

ogy with multi-layer, co-fired ceramic construction featuring

built-in isolated power and ground planes. These planes provide

lower overall resistance/inductance through power and ground

paths which minimize voltage drops during periods of heavy

switching. These isolated planes also help sustain supply volt-

age during dose rate events, thus preventing rail span collapse.

Flatpacks are available with up to 304 leads; PGAs are available

with up to 280 leads. UTMC’s flatpacks feature a non-conduc-

tive tie bar that helps maintain lead integrity through test and

handling operations. In addition to the packages listed in Table

2, UTMC offers custom package development and package tool-

ing modification services for individual requirements.

PACKAGE TYPE/LEADCOUNT1

Flatpack

84

132

172

196

224

256

304

PGA2

84

120

144

208

280

UTR25

X

X

X

X

X

X

X

Table 2. Packages

UTR35 UTR50

X

X

X

X

X

X

X

X

X

X

X

X

X

X

UTR75 UTR100 UTR150 UTR200

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Notes:

1. The number of device I/O pads available may be restricted by the selected package.

2. PGA packages have one additional non-connected index pin (i.e., 144 + 1 index pin = 145 total package pins for the 144 PGA).

Contact UTMC for specific package drawings.

2

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