ICS1574B データシートの表示（PDF） - Integrated Circuit Systems

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ICS1574B

User Programmable Laser Engine Pixel Clock Generator

Integrated Circuit Systems 

ICS1574B

Pin Configuration

PCLKEN 1

XTAL1 2

XTAL2 3

DATCLK 4

VSS 5

VSS 6

PCLK 7

(Do Not Connect) Reserved 8

16 DATA

15 HOLD

14 TEST (Connect to VSS))

13 VDD

12 VDDO

11 Reserved (Do Not Connect)

10 Reserved (Do Not Connect)

9 Reserved (Do Not Connect)

16-Pin Skinny SOIC

Pin Descriptions

PIN NUMBER

7

1

2

3

4

16

15

14

8, 9, 10, 11

13

12

5, 6

PIN NAME

PCLK

PCLKEN

XTAL1

XTAL2

DATCLK

DATA

HOLD

Test

Reserved

VDD

VDDO

VSS

DESCRIPTION

Pixel clock output.

PCLK Enable (Input).

Quartz crystal connection 1 / external reference frequency input.

Quartz crystal connection 2.

Data Clock (Input).

Serial Register Data (Input).

HOLD (Input).

Test. (Must be connected to VSS.)

Reserved. (Do Not Connect.)

PLL system power (+5V. See application diagram).

Output stage power (+5V).

Device ground. (Both pins must be connected.)

2

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